uPD780065 Subseries PUM - Renesas Electronics

CHAPTER 7 8-BIT TIMER/EVENT COUNTER
(2) Operation after compare register transition during timer count operation
If the value after 8-bit compare register 5n (CR5n) is transmitted is smaller than the value of 8-bit counter 5n
(TM5n), TM5n continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after CR5n
is smaller than value (N) before transition, it is necessary to restart the timer after transiting CR5n.
Figure 7-14. Timing after Compare Register Transition during Timer Count Operation
Count pulse
CR5n
TM5 count value
Caution Except when the TI5n input is selected, always set TCE5n = 0 before setting the stop state.
Remarks 1. N > X > M
2. n = 0, 1
(3) TM5n (n = 0, 1) reading during timer operation
When reading TM5n during operation, select count clock having high/low level wave form longer than two cycles
of CPU clock because count clock stops temporary. For example, in the case where CPU clock (fCPU) is fx, when
the selected count clock is fx/4 or below, it can be read.
Remark n = 0, 1
N M
X–1 X FFH 00H 01H 02H
Preliminary User’s Manual U13420EJ2V0UM00
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