uPD780065 Subseries PUM - Renesas Electronics

CHAPTER 6 16-BIT TIMER/EVENT COUNTER
(2) 16-bit timer capture/compare register 00 (CR00)
CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether
it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register
0 (CRC0).
• When CR00 is used as a compare register
The value set in the CR00 is constantly compared with the 16-bit timer/counter 0 (TM0) count value, and an
interrupt request (INTTM00) is generated if they match. It can also be used as the register which holds the
interval time then TM0 is set to interval timer operation, and as the register which sets the pulse width in the
PWM operating mode.
• When CR00 is used as a capture register
It is possible to select the valid edge of the TI00/TO0/P20 pin or the TI01/P21 pin as the capture trigger. Setting
of the TI00 or TI01 valid edge is performed by means of prescaler mode register 0 (PRM0).
If CR00 is specified as a capture register and capture trigger is specified to be the valid edge of the TI00/TO0/
P20 pin, the situation is as shown in Table 6-3. On the other hand, when capture trigger is specified to be
the valid edge of the TI01/P21 pin, the situation is as shown in Table 6-4.
Table 6-3. TI00/TO0/P20 Pin Valid Edge and Capture/Compare Register Capture Trigger
ES01 ES00 TI00/TO0/P20 Pin Valid Edge CR00 Capture Trigger CR01 Capture Trigger
0 0 Falling edge Rising edge Rising edge
0 1 Rising edge Falling edge Falling edge
1 0 Setting prohibited Setting prohibited Setting prohibited
1 1 Both rising and falling edges No capture operation Both rising and falling edges
Table 6-4. TI01/P21 Pin Valid Edge and Capture/Compare Register Capture Trigger
ES11 ES10 TI01/P21 Pin Valid Edge CR00 Capture Trigger
0 0 Falling edge Falling edge
0 1 Rising edge Rising edge
1 0 Setting prohibited Setting prohibited
1 1 Both rising and falling edges Both rising and falling edges
CR00 is set by a 16-bit memory manipulation instruction.
After RESET input, the value of CR00 is undefined.
Cautions 1. Set a value other than 0000H in CR00. This means 1-pulse count operation cannot be
performed when CR00 is used as an event counter. However, in the free-running mode and
in the clear mode using the valid edge of TI00, if 0000H is set to CR00, an interrupt request
(INTTM00) is generated following overflow (FFFFH).
2. When P20 is used as the valid edge of TI00, it cannot be used as timer output (TO0).
Moreover, when P20 is used as TO0, it cannot be used as the valid edge of TI00.
Preliminary User’s Manual U13420EJ2V0UM00
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