Two-wire Serial EEPROMs AT24C128 AT24C256 - Atmel Corporation
Two-wire Serial EEPROMs AT24C128 AT24C256 - Atmel Corporation
Two-wire Serial EEPROMs AT24C128 AT24C256 - Atmel Corporation
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Figure 2. Bus Timing (SCL: <strong>Serial</strong> Clock, SDA: <strong>Serial</strong> Data I/O ® )<br />
Figure 3. Write Cycle Timing (SCL: <strong>Serial</strong> Clock, SDA: <strong>Serial</strong> Data I/O)<br />
SCL<br />
SDA<br />
WORDn<br />
8th BIT<br />
Note: 1. The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.<br />
8 <strong>AT24C128</strong>/256<br />
ACK<br />
STOP<br />
CONDITION<br />
t wr (1)<br />
START<br />
CONDITION<br />
0670T–SEEPR–3/07
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