AVR32107: Using TWI as a Master on the AVR32 - Atmel Corporation

<strong>AVR32107</strong>: <strong>Using</strong> <strong>TWI</strong> <strong>as</strong> a M<strong>as</strong>ter on the AVR32
Features
- Compatible with Philips' I 2 C protocol
- M<strong>as</strong>ter transmitter mode
- M<strong>as</strong>ter receiver mode
- 7-bit slave address – up to 127 devices on the same bus
- Normal (100kbps) and F<strong>as</strong>t (400kbps) operation
- Interrupt driven communication
- Sequential read and write operation
- Compatible with Standard Two-Wire Serial Memory
- Currently only m<strong>as</strong>ter mode is supported
1 Introduction
The AVR®32 microcontroller communicate <strong>as</strong> the m<strong>as</strong>ter on a <strong>TWI</strong> bus (Philips’
I2C compatible Two-Wire Interface). Up to 127 <strong>TWI</strong> devices can be connected to
each bus. The bus is half-duplex, and the current m<strong>as</strong>ter device initiates transfers
both ways.
Figure 1.1: Conceptual schematics
MASTER
DATA
CLOCK
SLAVE #1
SLAVE #2
SLAVE #127
32-bit
Microcontrollers
Application Note
Rev. 32011A-AVR-04/06

2 Functional description
2.1 Electrical interconnection
2.2 Wired AND
2 <strong>AVR32107</strong>
The <strong>TWI</strong> bus consists of two lines, one for data and one for the clock signal (and
possibly one for ground). Both bus lines are connected to the positive supply voltage
through pull-up resistors. When a device wants to output a logical 0, it drives the bus
line low and for logical 1, the output is tri-stated. In this way the device relies on the
pull-up resistor to pull the line high. This technique is often referred to <strong>as</strong> wired AND.
This is described in further detail in chapter 2.2.
Figure 2.1: Electrical schematics
MASTER
2.3 Bus events: START and STOP conditions
2.4 Acknowledgement
TWD
TWCK
VDD
SLAVE #1 SLAVE #2
Both lines in the <strong>TWI</strong> bus are connected to the power source with pull-up resistors. As
a result, both lines on the bus will go high, if no device is driving the bus. The wired-
AND is a result of that the devices currently transmitting on the bus rele<strong>as</strong>es it when
logical 1 is to be transmitted, and only drives the bus when they are to transmit logical
0. Thus, the signal on the bus will be the result of an AND operation on all bits
currently transmitted, and a device transmitting 0 will dominate over one transmitting
1.
In order to either start or stop a transmission, START and STOP conditions are
issued. These conditions are defined <strong>as</strong>:
• START: The data line is driven low while by the m<strong>as</strong>ter the clock line is high. Then
the m<strong>as</strong>ter drives the clock line low.
• STOP: The clock line is rele<strong>as</strong>ed (driven high), and then the m<strong>as</strong>ter rele<strong>as</strong>es the
data line.
The start condition for a <strong>TWI</strong> device may in some c<strong>as</strong>es be defined by the m<strong>as</strong>ter
driving the data line low. The m<strong>as</strong>ter will then drive the clock line low, independent the
definition of the start condition. Whatever is the c<strong>as</strong>e, these transitions will generate a
START condition.
Whenever the m<strong>as</strong>ter is transferring data to a slave, every byte sent h<strong>as</strong> to be
acknowledged by the slave. This is done by pulling the data line low after each byte
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2.5 Transfer format
2.6 Transmitting data
2.6.1 Transmission initialization
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<strong>AVR32107</strong>
transmission. If the slave acknowledges the data, this is read <strong>as</strong> ACK (acknowledge)
by the m<strong>as</strong>ter. But if the slave fails to acknowledge, for some re<strong>as</strong>on or another, the
line is not pulled down and is read <strong>as</strong> NACK (not acknowledged) from the m<strong>as</strong>ter's
point of view.
Data is transferred MSB first, and each character is 8 bit long. There is no parity
check, but every character must be followed by an acknowledgement. The data line
(TWD) must remain stable while the clock line (TWCK) is high to ensure data
consistency. The exceptions from this are the START condition and STOP condition.
Every transmission is initiated by a START condition. When the m<strong>as</strong>ter wants to end
the transmission, a STOP condition is transmitted. Repeated START conditions can
be used if the m<strong>as</strong>ter wishes to address other devices without risking losing the bus
to another m<strong>as</strong>ter.
As <strong>TWI</strong> is half duplex, data can be written from the m<strong>as</strong>ter to the slave or vice versa.
These two operations have a lot in common, but there are also some differences.
These two operations are described in this chapter.
To initiate a <strong>TWI</strong> transfer, a m<strong>as</strong>ter must initiate a START condition. After the m<strong>as</strong>ter
initiates a START condition, it sends a 7-bit slave address. The 8 th bit indicates the
transfer direction (write or read). Read is logical 1, while write is 0. After the first byte,
the m<strong>as</strong>ter will rele<strong>as</strong>e the data line, allowing a slave to drive it low. If a device on the
bus recognizes its own address, it will pull down the bus on the following cycle, giving
the m<strong>as</strong>ter an ACK. In Figure 2.1 a m<strong>as</strong>ter tries to access a device with address (id)
0x73 with a read operation and the slave acknowledges the request.
The Figure 2.1 shows how data is read on the <strong>TWI</strong> bus. When the clock is high, the
data line must be stable and no transitions may be made. If such transitions do
happen, unspecified behavior may occur.
Figure 2.1: Transfer initialization
1 1 1
1 1 1
TWD
0 0
0
TWCK
START
CONDITION
THE <strong>TWI</strong> MASTER INITIATES THE
TRANSMISSION BY SENDING THE ADDRESS
(0x73) FOLLOWED BY A READ COMMAND
When a slave h<strong>as</strong> been accessed, data is transmitted according to the read/write
instruction in the initialization ph<strong>as</strong>e.
ACK
3

2.6.2 Read request
2.6.3 Write request
4 <strong>AVR32107</strong>
Before reading data from the slave device, a command may be given. This command
can either be 0, 1, 2 or 3 bytes long. Each sequential command is followed by an
acknowledgement by the slave in the same manner <strong>as</strong> in the initialization of the
transfer. This command is device specific and may sometimes be referred to <strong>as</strong> an
address for some devices.
After the command sequence of a transmission, the slave device is responsible for
the data line and drives it. The m<strong>as</strong>ter is still responsible for driving the clock line. As
the m<strong>as</strong>ter is responsible for driving the clock line, no acknowledge bit is p<strong>as</strong>sed after
a byte transfer. The most significant bit is always transmitted first. The slave will not
change the data line while the clock is high. This is extremely important, <strong>as</strong> this may
generate a START or STOP condition.
Figure 2.2: Command sequence
1
1
1 1 1
TWD
TWCK
0
0 0
MASTER SENDS
COMMAND 0xA7
A complete read sequence is found in Figure 2.2. The m<strong>as</strong>ter tries to contact a node
with address 0x53 with a read instruction. The slave responds by acknowledging this.
Then the slave puts out 0x2A <strong>as</strong> an answer to that request. In turn, the m<strong>as</strong>ter
acknowledges this and sends out a STOP condition, finalizing the transfer.
Figure 2.2: A complete read sequence (without command sequence)
TWD
TWCK
MSB
LSB
ACK
MSB
START STOP
The m<strong>as</strong>ter issues a read request
to device 0x53
From
slave
The slave resonds with 0x2A
0
ACK
LSB
ACK
From
m<strong>as</strong>ter
If a write request is made to a slave during initialization, the m<strong>as</strong>ter is responsible for
driving the data line and feeding the slave with bytes. After each transmission of a
byte, the slave must acknowledge the byte sent. This is done in the same matter <strong>as</strong>
acknowledging a transfer request, described in chapter 2.4.1.
The transmission ends when the transmitter stops sending, or if the transmitter does
not receive an ACK for the transmitted character. The m<strong>as</strong>ter will then set a STOP
condition on the bus, rele<strong>as</strong>ing it, or initiate a new session by sending another START
condition.
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32011A-AVR-04/06
Figure 2.3: A write operation
TWD
TWCK
2.7 More than one m<strong>as</strong>ter - arbitration
2.8 Usage
3 Package information
MSB
LSB
ACK
MSB
<strong>AVR32107</strong>
START STOP
The m<strong>as</strong>ter issues a write request
to device 0x4B
From
slave
The m<strong>as</strong>ter writes 0x22 to the slave
Only one m<strong>as</strong>ter can be in control of the communication on the bus at any time. No
other device will interfere with an ongoing transmission. If the bus is in use and
another m<strong>as</strong>ter starts driving the bus lines, hazardous behavior may occur. The
m<strong>as</strong>ter currently in control is providing the clock signal on the bus.
However, if two m<strong>as</strong>ters initiate a START condition simultaneously, they will both start
transmitting clock and data signal. To avoid corruption of data, one of them h<strong>as</strong> to
switch to idle or slave mode. This problem is solved through arbitration; both (or all)
m<strong>as</strong>ters start transmitting, but the moment one of them discovers that the TWD line is
driven by some other m<strong>as</strong>ter, it will stop transmitting, and go to idle or slave mode.
The mode is dependent of the features supported by the <strong>TWI</strong> m<strong>as</strong>ter. A consequence
of the wired-AND logic is that if 1 and 0 is transmitted on a bus wire simultaneously,
the bus will read 0. Every m<strong>as</strong>ter transmitting data will read the value on the bus to
see if they really are driving the bus. As soon <strong>as</strong> a device tries to transmit 1, but the
bus reads 0, it will know that some other device is transmitting, and switch to slave or
idle mode.
The result is that the m<strong>as</strong>ter sending the lowest address character will win the bus (if
two or more m<strong>as</strong>ters are trying to address the same device, the arbitration will
continue in the direction bit, and possibly the data bits). The AVR32 microcontroller is
unable to enter slave mode. Thus, when it loses the bus, it will enter idle mode until a
STOP condition is transmitted on the bus, signaling that the m<strong>as</strong>ter currently in
control of the bus is done. When a STOP condition is detected, and the AVR32 wants
to communicate on the bus, a START condition is immediately transmitted.
Before any data can be sent on the <strong>TWI</strong> bus, it must first be initialized. Then a
specific device can be probed to check whether it is responding or not. It is then also
possible to receive or send data. The functions for these operations are described in
chapter 2.6.1.
Baudrate(s) for your <strong>TWI</strong> slave is described in the appropriate dat<strong>as</strong>heet for your
device. It is important to select the correct baudrate, <strong>as</strong> it is the m<strong>as</strong>ter's responsibility
to drive the clock line.
Included with the application note is a driver package. This package contains drivers,
example code and documentation.
LSB
ACK
From
slave
5

3.1 Drivers
3.2 Examples
3.3 Documentation
4 Further reading
6 <strong>AVR32107</strong>
Drivers are available in the package. These drivers are written to be independent of a
specific compiler and are successfully tested on gcc and IAR Embedded Workbench.
Examples are available from the corresponding driver package. All functionality is
divided into libraries and an example that utilizes the library.
Function specific documentation is available in the package. Refer to readme.html in
the source code directory.
The AVR32 <strong>TWI</strong> also h<strong>as</strong> support for Direct Memory Access (DMA) and interruptdriven
communication. These two concepts are described in two other Application
notes, namely AVR32108 title and AVR32109 title respectively.
32011A-AVR-04/06

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