Case Studies of All-Surface Inspection in a - Sematech
Case Studies of All-Surface Inspection in a - Sematech
Case Studies of All-Surface Inspection in a - Sematech
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<strong>Case</strong> <strong>Studies</strong> <strong>of</strong> <strong>All</strong>-<strong>Surface</strong><br />
<strong>Inspection</strong> <strong>in</strong> a 3DI-TSV R&D<br />
Environment<br />
Rolf Shervey<br />
Sr. Applications Eng<strong>in</strong>eer<br />
Rudolph Technologies, Inc.
Equipment <strong>in</strong> Albany<br />
Explorer <strong>Inspection</strong> Cluster<br />
•AXi 935 for top surface<br />
•E30 for wafer edge-bevel<br />
•B30 for wafer backside<br />
•Installed <strong>in</strong> 1st half <strong>of</strong> 2008
<strong>All</strong> <strong>Surface</strong> <strong>Inspection</strong> – <strong>Case</strong> <strong>Studies</strong><br />
Defect <strong>in</strong>spection (pre- and post-bond)<br />
• Defects at bond <strong>in</strong>terface can break wafers<br />
• Edge bevel chips/slip can create cleave l<strong>in</strong>es dur<strong>in</strong>g<br />
bond<strong>in</strong>g<br />
AXi 935 <strong>All</strong>-<strong>Surface</strong> System is used to <strong>in</strong>spect top, bottom,<br />
and edge bevel:<br />
• Identify defects that will break wafers & impact yield<br />
• pre-bonder<br />
• post-bonder<br />
• before wafer th<strong>in</strong>n<strong>in</strong>g (gr<strong>in</strong>d<strong>in</strong>g)<br />
3
FRONT-SIDE INSPECTION
Misaligned via pattern <strong>in</strong> BF <strong>in</strong>spection<br />
Images<br />
courtesy <strong>of</strong><br />
SEMATECH<br />
AXi <strong>in</strong>spection <strong>of</strong> metal via-<br />
patterned wafers found<br />
misalignment <strong>of</strong> via<br />
pattern.<br />
5
<strong>All</strong> <strong>Surface</strong> <strong>Inspection</strong> – <strong>Case</strong> <strong>Studies</strong><br />
Miss<strong>in</strong>g vias<br />
• Follow<strong>in</strong>g M1 oxide deposition,<br />
miss<strong>in</strong>g vias <strong>in</strong> the alignment<br />
marks used for lithography were<br />
observed<br />
• Subsequent <strong>in</strong>spection revealed<br />
multiple miss<strong>in</strong>g vias<br />
• Used the Rudolph Axi935 all-<br />
surface <strong>in</strong>spection tool to gather<br />
statistics.<br />
• Miss<strong>in</strong>g vias are ~10X more<br />
probable on square vias than on<br />
round or octagonal vias<br />
• Suggests that stress plays a role<br />
• One s<strong>in</strong>gle miss<strong>in</strong>g VSPM via<br />
(1/395,472) was observed on 2<br />
wafers subjected to 150°C anneal<br />
Slide courtesy Larry Smith - SEMATECH<br />
0% 1% 2% 3% 4% 5% 6%<br />
only after CMP 0% 1% 2% 3% 4% 5% 6%<br />
6<br />
½ <strong>of</strong> a VSPM alignment mark<br />
Image and <strong>in</strong>spection data from Rudolph AXi<br />
Miss<strong>in</strong>g 46EBL052SJA3; Via Defect<br />
46EBL052SJA3;<br />
defect% Density<br />
defect%<br />
4x4 (8x8) TSV arrays,<br />
4,5,6 µm diameter; square, octagonal, and round<br />
8x8_5um_P25um_round<br />
8x8_5um_P25um_round<br />
8x8_5um_P20um_round<br />
8x8_5um_P20um_round<br />
8x8_5um_P15um_round<br />
8x8_5um_P15um_round<br />
4x4_4um_P8um_round<br />
4x4_4um_P8um_round<br />
4x4_5um_P10um_round<br />
4x4_5um_P10um_round<br />
4x4_6um_P12um_round<br />
4x4_6um_P12um_round<br />
4x4_4um_P8um_oct<br />
4x4_4um_P8um_oct<br />
4x4_5um_P10um_oct<br />
4x4_5um_P10um_oct<br />
4x4_6um_P12um_oct<br />
4x4_6um_P12um_oct<br />
4x4_4um_P8um_square<br />
4x4_4um_P8um_square<br />
4x4_5um_P10um_square<br />
4x4_5um_P10um_square<br />
4x4_6um_P12um_square<br />
4x4_6um_P12um_square
<strong>All</strong> <strong>Surface</strong> <strong>Inspection</strong> – <strong>Case</strong> <strong>Studies</strong><br />
Slide courtesy Larry Smith - SEMATECH<br />
Miss<strong>in</strong>g via – failure analysis<br />
• Top ~3 microns <strong>of</strong> copper miss<strong>in</strong>g <strong>in</strong> the TSV<br />
• Stress related – Copper anneal modified<br />
• AXi 935 useful to detect, quantify, and <strong>in</strong>spect TSV defects<br />
Miss<strong>in</strong>g via<br />
7<br />
Delam<strong>in</strong>ation?
EDGE-BEVEL INSPECTION
E30 System Overview<br />
Edge Top<br />
Camera<br />
• Darkfield and Brightfield <strong>in</strong>spection and metrology<br />
• Multiple EBR l<strong>in</strong>e metrology <strong>in</strong> zones 1-4<br />
• Brightfield color image defect capture driven by darkfield sensitivity<br />
• Advanced defect b<strong>in</strong>n<strong>in</strong>g based on defect attributes<br />
• Color, <strong>in</strong>tensity, size, area, location, contrast strength, illum<strong>in</strong>ation type<br />
• B<strong>in</strong> specific defects can be further classified by an Edge ADC eng<strong>in</strong>e<br />
• High throughput capable up to 100WPH<br />
9<br />
Edge Normal<br />
Camera
Wafer Edge Zones and Defects <strong>of</strong> Interest<br />
6mm<br />
~<br />
~<br />
Zone 1<br />
Pattern side<br />
Top Edge<br />
~<br />
Wafer Edge Exclusion (WEE)<br />
~<br />
Zone 1 Typical <strong>Inspection</strong> Criteria<br />
Zones Multi-film 2, 3 & 4 EBR Typical / EEW <strong>Inspection</strong> Zone Metrology5<br />
Criteria<br />
EBR centricity with 0.1 mm resolution<br />
Backside R<strong>in</strong>se EBR Bottom metrology <strong>of</strong> Wafer<br />
Supported <strong>in</strong> zones 2 - 4<br />
Coat<strong>in</strong>g Problems, Chips, Cracks, Mechanical<br />
Zone Blisters, Residues, Coat<strong>in</strong>g Problems<br />
Damage 5 Typical <strong>Inspection</strong> Criteria<br />
Particles, Visual defects > 5µm<br />
Resolution Mechanical > 4umDamage,<br />
Sta<strong>in</strong>s<br />
Delam<strong>in</strong>ation, Peel<strong>in</strong>g, Particles<br />
Blisters, > 3µm<br />
Delam<strong>in</strong>ation, Peel<strong>in</strong>g, Particles<br />
> 2µm<br />
> 1µm<br />
Distance from Apex with 0.1 mm resolution<br />
Up to 3600 measurement po<strong>in</strong>ts possible<br />
Bevel Transition<br />
10<br />
Wafer Bevel<br />
~ 2-4mm<br />
(pr<strong>of</strong>ile shape<br />
dependent)<br />
Zone 2<br />
Top Bevel<br />
Zone 3<br />
Apex<br />
Zone 4<br />
Bottom Bevel
<strong>All</strong> <strong>Surface</strong> <strong>Inspection</strong> – <strong>Case</strong> <strong>Studies</strong><br />
Bonded wafer pair re-entry to CMOS fab<br />
• SEMI M1.15 def<strong>in</strong>es wafer diameter, thickness, notch, bevel edge<br />
(100s <strong>of</strong> parameters…)<br />
• Bonded, th<strong>in</strong>ned, and edge-trimmed wafers challenge SEMI M1.15<br />
• Other SEMI standards affected<br />
• SEMI E47.1 (FOUP)<br />
• SEMI M31 (FOSB)<br />
• SEMI E15.1 – Load ports<br />
• SEMI M1 – Notch<br />
• SEMI T7 – Wafer identification<br />
• Potential issues:<br />
• Pre-aligner<br />
• Wafer <strong>in</strong>dexer/mapper<br />
• Double stack, cross-slot errors<br />
• Edge bevel scatter<strong>in</strong>g<br />
• Carrier damage to BWP<br />
Slide courtesy Andy Rudack - SEMATECH<br />
11
Bonded Wafer Pair Metrology & Defect<br />
<strong>Inspection</strong><br />
SEMATECH Phase I‐<br />
Bonded Wafer Pair<br />
Mechanical Test<strong>in</strong>g:<br />
Edge <strong>in</strong>spection on E30<br />
successfully completed<br />
May 29, 2009.<br />
12
Th<strong>in</strong>ned Top Wafer (via wafer)<br />
Edge-Top (ET) <strong>in</strong>spection<br />
<strong>of</strong> edge trimmed via<br />
wafer.<br />
E30 proven to detect<br />
critical defects <strong>in</strong> sub-<br />
contracted edge trim<br />
process.<br />
Scallop marks<br />
(chips) detected <strong>in</strong><br />
the trim l<strong>in</strong>e<br />
Bottom wafer (handle<br />
wafer)<br />
has gr<strong>in</strong>d tracks from<br />
saw<br />
13<br />
(top<br />
wafer)
Application s<strong>of</strong>tware for edge trim monitor<strong>in</strong>g – adapted<br />
from EBR metrology<br />
Edge Top<br />
Camera<br />
wafer<br />
open space<br />
Acquire <strong>in</strong>dividual brightfield<br />
Edge Top images around full<br />
circumference<br />
Stitch and compress the Edge<br />
Top images <strong>in</strong>to a s<strong>in</strong>gle<br />
composite image<br />
F<strong>in</strong>d the EBR l<strong>in</strong>es<br />
• Rudolph’s exist<strong>in</strong>g EBR metrology s<strong>of</strong>tware for the edge can<br />
be adapted to monitor edge trim process.<br />
14
TSV METROLOGY<br />
DEVELOPMENT<br />
PARALLEL EXPERIMENTS AT RUDOLPH’S<br />
DEVELOPMENT FACILITIES
Optical <strong>in</strong>spection – Defects <strong>of</strong> Interest<br />
Cover Glass Bottom Defect<br />
Cover Glass<br />
Silicon Via Depth Silicon Thickness<br />
Via Bottom Defect<br />
Via Wall Defect<br />
Cover Glass Top Defect<br />
Via Bottom Diameter<br />
Via Top Diameter<br />
16<br />
Cover Glass Thickness
Via Wall and Bottom Defect <strong>Inspection</strong><br />
Defect Images – 10X Via Bottom<br />
17
Via Top and Bottom Diameter Measurement<br />
Results – Via Too Small and Via Too Large<br />
• Vias reported as Too Small due to defects <strong>in</strong> the<br />
vias<br />
• Vias reported as Too Large are actually larger than<br />
the limits<br />
18
NEAR-INFRARED (NIR)<br />
INSPECTION EXPERIMENTS*<br />
ON RUDOLPH AXI PLATFORM<br />
*NOTE: EXPERIMENTS ONLY, NO COMMERCIAL PLANS AT THIS<br />
TIME.<br />
Experiments conducted <strong>in</strong> conjunction with<br />
SEMATECH 3DIC Group
NIR Prototype Optics<br />
• Bonded wafer pair <strong>in</strong>terface<br />
• Must image through top wafer, up to<br />
775 micron thick (opaque <strong>in</strong> visible)<br />
• Silicon is transparent <strong>in</strong> NIR/SWIR<br />
• Prototype NIR optics were<br />
<strong>in</strong>stalled on SEMATECH AXi 935<br />
system<br />
20<br />
NIR SWIR<br />
1000 1700
Configurations – Design <strong>of</strong> Experiments<br />
1. Nom<strong>in</strong>al: Exist<strong>in</strong>g CMOS camera / strobe lamp<br />
A. Current camera<br />
B. Available, current design, high-<strong>in</strong>tensity xenon-tungsten stroboscopic<br />
illum<strong>in</strong>ation. Broadband light: 400nm – 1300nm+<br />
2. Exist<strong>in</strong>g CMOS camera / halogen source<br />
A. Current camera (same as 1, A.)<br />
B. Constant-on illum<strong>in</strong>ation source: requires start/stop vs. cont<strong>in</strong>uous<br />
motion <strong>in</strong>spection. Throughput hit.<br />
3. IR camera / halogen<br />
A. NIR-specific camera (InGaAs, InSb or similar IR FPA). High cost.<br />
B. (Same as 2, B.)<br />
4. IR camera / strobe lamp<br />
A. (same as 3, A.)<br />
B. This would have the advantage <strong>of</strong> strobe-based, cont<strong>in</strong>uous motion<br />
<strong>in</strong>spection.<br />
21
Slide courtesy <strong>of</strong> SEMATECH<br />
22<br />
This is what<br />
we might<br />
expect to see<br />
<strong>in</strong> NIR with a<br />
misalignment.
#1: CMOS Camera / Xe Strobe Light Source<br />
5X Raw image through 775um Si<br />
Advantages<br />
1. Current camera & available<br />
stroboscopic light source. Could be<br />
used for high-speed <strong>in</strong>spection.<br />
2. Hardware costs are lower.<br />
Disadvantages<br />
1. Dark image / low photon quantity.<br />
2. Extra image process<strong>in</strong>g used to<br />
boost signal has a possible<br />
throughput impact & technical<br />
challenges.<br />
23
#2: CMOS Camera / Halogen (DC) Light Source<br />
5X Raw image through 775um Si<br />
Advantages<br />
1. Current camera.<br />
2. Hardware costs are still lower than IR<br />
camera.<br />
3. Image process<strong>in</strong>g may not be<br />
required.<br />
Disadvantages<br />
1. Start/stop <strong>in</strong>spection only, because<br />
light source is “constant on”.<br />
2. Some <strong>in</strong>tegration costs to develop &<br />
qualify new light source.<br />
24
#3: IR Camera / Halogen Source<br />
20X Raw image through 775um Si<br />
Advantages<br />
1. Best quantity <strong>of</strong> light.<br />
2. Good overall image quality.<br />
3. Image process<strong>in</strong>g may not be<br />
required.<br />
Disadvantages<br />
1. Pixel scale is 3.6x CMOS camera.<br />
(0.5um @ 20X on CMOS = 1.8um on<br />
IR camera)<br />
2. High cost camera.<br />
3. Some <strong>in</strong>tegration costs to develop &<br />
qualify new light source.<br />
25
#4: IR Camera / 4400 strobe<br />
Not able to acquire<br />
images <strong>in</strong> this<br />
configuration because<br />
<strong>of</strong> camera tim<strong>in</strong>g<br />
configuration.<br />
Needs further<br />
development before<br />
experiments can be<br />
performed.<br />
Theoretical Advantages<br />
1. Good quantity <strong>of</strong> light – middle<br />
ground.<br />
2. Reta<strong>in</strong> high-speed, stroboscopic &<br />
cont<strong>in</strong>uous motion capabilities.<br />
3. Image process<strong>in</strong>g may not be<br />
required.<br />
Theoretical Disadvantages<br />
1. Pixel scale is 3.6x CMOS camera.<br />
(0.5um @ 20X on CMOS = 1.8um on<br />
IR camera)<br />
2. High cost camera.<br />
26
Results<br />
What the camera “sees” processed image<br />
27<br />
Wafer<br />
bond<strong>in</strong>g<br />
defects <strong>of</strong><br />
<strong>in</strong>terest<br />
(DOI) shown<br />
should be<br />
captured by<br />
standard<br />
<strong>in</strong>spection<br />
algorithm.
Conclusions & Future Work on NIR<br />
• This k<strong>in</strong>d <strong>of</strong> metrology is currently be<strong>in</strong>g done by<br />
destructive cross-section SEMs, or by manual IR<br />
microscope review.<br />
• Would it be <strong>in</strong>terest<strong>in</strong>g to have <strong>in</strong>-l<strong>in</strong>e and production<br />
worthy automated metrology capability to measure for<br />
overlay alignment and process-specific adder defects so<br />
that improvements can be driven <strong>in</strong>to the bond<strong>in</strong>g and<br />
related processes, and potential yield killers caught<br />
earlier <strong>in</strong> this very deep TSV manufactur<strong>in</strong>g process?<br />
• What is the required Cost-<strong>of</strong>-Ownership for this tool?<br />
28
Summary<br />
1. The AXi 935 <strong>All</strong>-<strong>Surface</strong> <strong>Inspection</strong> platform has<br />
demonstrated capability for bonded wafer pair metrology,<br />
<strong>in</strong>clud<strong>in</strong>g bonded, th<strong>in</strong>ned, and edge trimmed wafers<br />
2. The Rudolph AXi 935 + E30/B30 <strong>All</strong>-<strong>Surface</strong> <strong>Inspection</strong><br />
System has proven to be a useful tool for support<strong>in</strong>g 3D<br />
<strong>in</strong>terconnect and TSV research.<br />
3. Rudolph ga<strong>in</strong>ed important <strong>in</strong>sights <strong>in</strong>to 3DIC/TSV<br />
manufactur<strong>in</strong>g market needs and benefited from the<br />
unique environment & work<strong>in</strong>g relationship with<br />
SEMATECH dur<strong>in</strong>g the conduct <strong>of</strong> these experiments.<br />
29
Acknowledgements<br />
SEMATECH 3D Team<br />
Tawfeeq Alzaben<br />
Sitaram Arkalgud<br />
Raymond Caramto<br />
Jose Colon<br />
John Hudnall<br />
Gary Knodler<br />
Jerry Mase<br />
Steve Olson<br />
Jamal Qureshi<br />
Andrew C. Rudack<br />
Pratibha S<strong>in</strong>gh<br />
Larry Smith<br />
Susan Smith<br />
Travis Smith<br />
Chris Taylor<br />
Weng-Hong Teh<br />
Bryan Thomas<br />
30
Rudolph’s Total Solution for 3DIC/TSV Manufactur<strong>in</strong>g<br />
Process<br />
<strong>Inspection</strong> /<br />
Metrology<br />
Specific criteria<br />
Solution<br />
Via Etch or Drill<br />
Via depth, Via<br />
CD, sidewall<br />
defect<br />
NSX 320<br />
With laser<br />
sensor (>20u)<br />
High‐res 3D<br />
(
Rudolph Technologies Confidential<br />
Thank You!<br />
32<br />
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