Introduction to PCB Design Cadence PCB Design Tools

Introduction to PCB Design Cadence PCB Design Tools Introduction to PCB Design Cadence PCB Design Tools

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Introduction to PCB Design Cadence PCB Design Tools Jason Blankenberg Fouad Kiamilev University of Delaware CPEG 324 This document will illustrate how to create a simple Printed Circuit Board (PCB) using the suite of Cadence design tools. The manufacturing requirements have been adapted from the PCBexpress website. When a pad size or drill size is specified, it is important to remember that they will vary depending on the manufacturer. While this tutorial is specific for the Cadence tools used in this class, a good general tutorial is available online at http://alternatezone.com/electronics/ Planning the Project Before we start creating a PCB we need to know some things about it. 1. What is the purpose of the board? 2. What components do we need? 3. Where will the board be made? 4. How much time will it take to get it done? 5. How difficult is this board? The first two questions will be answered here and the third will impact some design decisions later. The last two are dependant on you.

<strong>Introduction</strong> <strong>to</strong> <strong>PCB</strong> <strong>Design</strong><br />

<strong>Cadence</strong> <strong>PCB</strong> <strong>Design</strong> <strong>Tools</strong><br />

Jason Blankenberg<br />

Fouad Kiamilev<br />

University of Delaware<br />

CPEG 324<br />

This document will illustrate how <strong>to</strong> create a simple Printed Circuit Board (<strong>PCB</strong>) using<br />

the suite of <strong>Cadence</strong> design <strong>to</strong>ols. The manufacturing requirements have been adapted<br />

from the <strong>PCB</strong>express website. When a pad size or drill size is specified, it is important <strong>to</strong><br />

remember that they will vary depending on the manufacturer. While this tu<strong>to</strong>rial is<br />

specific for the <strong>Cadence</strong> <strong>to</strong>ols used in this class, a good general tu<strong>to</strong>rial is available online<br />

at http://alternatezone.com/electronics/<br />

Planning the Project<br />

Before we start creating a <strong>PCB</strong> we need <strong>to</strong> know some things about it.<br />

1. What is the purpose of the board?<br />

2. What components do we need?<br />

3. Where will the board be made?<br />

4. How much time will it take <strong>to</strong> get it done?<br />

5. How difficult is this board?<br />

The first two questions will be answered here and the third will impact some design<br />

decisions later. The last two are dependant on you.


What is the purpose of the board?<br />

For this tu<strong>to</strong>rial we will be creating a simple board that will cover the abilities you will<br />

need <strong>to</strong> know for the board. To cover the basics, we need a board that uses: at least one<br />

discrete surface mount component, a component that uses through-hole mounting,<br />

transmission lines, SMA edge connec<strong>to</strong>rs and various capaci<strong>to</strong>rs and resis<strong>to</strong>rs. Generally<br />

the component selection would be based on the project requirements. We first need <strong>to</strong><br />

create a rough drawing or schematic of what we want <strong>to</strong> put <strong>to</strong>gether. Once we have that<br />

we can decide what components will be used. Here is the first sketch of a circuit for this<br />

design:


What components do we need?<br />

From there I began looking for components and expanding on what will actually be one<br />

the <strong>PCB</strong>. The easiest way <strong>to</strong> find components is <strong>to</strong> use companies like Digi-Key and<br />

Mouser Electronics and search their catalogs. Once some suitable parts are determined it<br />

is time <strong>to</strong> update the hand schematics. Other things will be required depending on the<br />

parts selected as well.


From the parts selected we need resis<strong>to</strong>rs and capaci<strong>to</strong>rs. There is also an LED included<br />

<strong>to</strong> have visual output, but also requires the use of a transis<strong>to</strong>r. A header is also included<br />

for use with a jumper. We then list the components we will be using.<br />

LVDS Driver and Receiver: DS90LV049TMT<br />

Quad Input XOR gate: 74LVQ86SC<br />

LED: C170TBKT<br />

47.5 OHM resis<strong>to</strong>r: ERJ-3EKF47R5V


100 OHM resis<strong>to</strong>r: ERJ-2RKF1000X<br />

3 pin Header: 87224-3<br />

.1 uF Capaci<strong>to</strong>r: ECJ-2VB1C104K<br />

.001 uF Capaci<strong>to</strong>r: ECJ-ZEB1E102K<br />

NMOS: BSS138TA<br />

Pin Tip Power Connec<strong>to</strong>rs: Black: J110-ND & Red: J109-ND<br />

SMA End Launch Connec<strong>to</strong>r: 142-0701-801<br />

Another design decision is the number of layers <strong>to</strong> use in the <strong>PCB</strong>. The LVDS<br />

driver/receiver suggests a minimum of 4 layers. This project does not require more layers<br />

than that, so we will make a 4 layer board. With the planes of the board described from<br />

<strong>to</strong>p <strong>to</strong> bot<strong>to</strong>m: High-speed signals, ground, power, signals. With this information we can<br />

begin constructing the board. This tu<strong>to</strong>rial will walk through the steps in a linear order. It<br />

is important <strong>to</strong> know that this is not always a linear process. There may be times when the<br />

design is changed or a component changed.<br />

Seting up the Tool Suite<br />

First, the environment needs <strong>to</strong> setup. This is accomplished by adding the <strong>Cadence</strong> <strong>to</strong>ols<br />

<strong>to</strong> your path. You can download and source this file <strong>to</strong> add the setup the path. The file<br />

needs <strong>to</strong> be sourced every time you log on <strong>to</strong> the system. You can locate the file here:<br />

http://www.ece.udel.edu/~blankenb/cpeg324/downloads/cadence_setup.source. Make a<br />

direc<strong>to</strong>ry for the tu<strong>to</strong>rial and then make several sub-direc<strong>to</strong>ries. Make direc<strong>to</strong>ries called<br />

pad, psm and dra. These will be used later <strong>to</strong> s<strong>to</strong>re different files of the project.<br />

Starting the Tool Suite<br />

For this tu<strong>to</strong>rial you will be starting the <strong>Cadence</strong> Project Manager which will provide you<br />

with the <strong>to</strong>ol flow for creating the <strong>PCB</strong>. Create a direc<strong>to</strong>ry that you want <strong>to</strong> keep you<br />

project files in. Enter that direc<strong>to</strong>ry and type:<br />

snorlax[45] [~/pcb/tu<strong>to</strong>rial/]> projmgr<br />

This will launch the Product Choice window. Choose the <strong>to</strong>p option, <strong>PCB</strong> <strong>Design</strong> Expert.<br />

This will then flash the <strong>Cadence</strong> splash screen and finally the <strong>PCB</strong> <strong>Design</strong> Expert: Project<br />

Manager.


Creating a New Project<br />

To start the design process we first must start a project. The project will create a .cpm<br />

file that does the project tracking. To start the project we click on the Create<br />

Library Project but<strong>to</strong>n in the Project Manager. This will bring up the New<br />

Project Manager Window. To continue past this page, select Non-DM and press<br />

the Next but<strong>to</strong>n. The choices between Data Managed and Non-Data Managed projects,<br />

choosing Non-DM will simplify our configuration. Data managed mode is used in shared<br />

project environments <strong>to</strong> allow multiple users <strong>to</strong> access the same projects while<br />

maintaining project integrity (similar <strong>to</strong> a CVS).


The next window in the wizard asks for a project name and a direc<strong>to</strong>ry. Because we<br />

started Project Manager in the direc<strong>to</strong>ry we want <strong>to</strong> use, it is already in the Location<br />

box. The Project Name for this exercise will be tu<strong>to</strong>rial.<br />

The next screen is used <strong>to</strong> add libraries <strong>to</strong> your project. For now we will skip this step<br />

and add a library later.


After clicking next, the project summary will be displayed. The configuration generated<br />

by the wizard can be checked. The project will be created by clicking the finish<br />

but<strong>to</strong>n.<br />

A progress box will be displayed. When it has finished, you should hopefully receive this<br />

message:


After you click OK, the Project Manager window should change <strong>to</strong> the Library<br />

Management (<strong>PCB</strong> Librarian Expert) Flow. If it does not, or you need <strong>to</strong><br />

switch between different <strong>to</strong>ols you can change the Project Manager window using the<br />

Flows menu and clicking on Library Management<br />

Setup the Paths for the Project<br />

We now need <strong>to</strong> setup cadence <strong>to</strong> use the files we created. This is done by setting the<br />

paths in <strong>Cadence</strong>. First open the Board <strong>Design</strong> flow and click on the Setup picture.


This will open this window:<br />

First click on the <strong>Tools</strong> tab and then select Allegro Setup. This will open a<br />

window called User Preference Edi<strong>to</strong>r where you can setup many different<br />

aspects of the project. We will only be changing some design paths. From the folder<br />

listing on the left choose the <strong>Design</strong>_paths folder. We will then change the value for<br />

padpath and psmpath.


Click the but<strong>to</strong>n with 3 dots next <strong>to</strong> the option you want <strong>to</strong> change. First<br />

padpadth: We must now enter the a path for where we will s<strong>to</strong>re our pads. Of the<br />

but<strong>to</strong>ns on the <strong>to</strong>p right of the screen, choose the right most one New(Insert).<br />

Use the 3 dot but<strong>to</strong>n again <strong>to</strong> open a file explorer, select the pad direc<strong>to</strong>ry you created<br />

earlier and then click OK until it is added <strong>to</strong> the padpath items window.<br />

Press OK <strong>to</strong> return <strong>to</strong> the User Preference Edi<strong>to</strong>r. Do the same for the psmpath. Then click<br />

OK in the User Preference Edi<strong>to</strong>r and the Project Setup window <strong>to</strong> apply the settings and<br />

close the windows.


Pad Stack<br />

The next step <strong>to</strong> creating a <strong>PCB</strong> is <strong>to</strong> design the pads that will be used for components.<br />

<strong>Cadence</strong> generally includes some standard pads but these have <strong>to</strong> be verified by you.<br />

Therefore it is normally easier and safer <strong>to</strong> make the pads yourself. The pads are created<br />

using a <strong>to</strong>ol called the Pad Stack Edi<strong>to</strong>r. To access this <strong>to</strong>ol you will need <strong>to</strong><br />

change the Flow again. This <strong>to</strong>ol can be launched from the Library Management flow of<br />

the Project Manager.<br />

There are many options in this window, including two tabs. The options will be described<br />

first and then we will create the pads based on data sheets for a few components.<br />

Type: Is this the style of pad you need <strong>to</strong> make, this depends on the component. Through<br />

drills all the way through the board. Single is just a single landing on the layer.<br />

Blind/Buried are pads that do not go all the way through the <strong>PCB</strong>.<br />

Units: This option specifies the units that you will use for this part. This is almost<br />

always mils.


Multiple drill: this allows for multiple drills holes in the same pad stack.<br />

Drill hole: The options in here allow for a plated or non-plated pad. Plated pads are<br />

used <strong>to</strong> make the electrical connections. A non-plated pad could be used as a mounting<br />

hole. The size of the drill hole is the diameter of the drill used for the component. The<br />

Offsets are used <strong>to</strong> specify a drill hole that is not in the center of the pad.<br />

Drill symbol: The figure is used <strong>to</strong> visually identify the pad. The character is<br />

unused. The width should be set <strong>to</strong> the size of the hole, this is not required but can be<br />

done.<br />

The next step is <strong>to</strong> move <strong>to</strong> the layers tab. This is where the information for the pads<br />

is really defined. This is the critical part of the pad stack edi<strong>to</strong>r. Depending on the type of<br />

pad (Through or Single) the layers tab will be different. This is because single type pads<br />

(also called surface mount) have no drill hole and therefore have no internal or bot<strong>to</strong>m<br />

layers. The different layers of the pad stack are Begin Layer, End Layer,<br />

SOLDERMASK, PASTEMASK, and FILMMASK. Once each layer is selected there are<br />

different parameters associated with each layer, they are Regular Pad, Thermal<br />

Relief, and Anti Pad.<br />

Layers:<br />

Begin Layer: Used <strong>to</strong> describe the size of the copper landing used for the pad. This is<br />

often referred <strong>to</strong> as the copper layer.<br />

Default Internal Layer: This is the default pad size for internal layers. This is<br />

used for through-hole mounting and vias. Keep this the same as the begin layer.<br />

End Layer: Used <strong>to</strong> describe the size of the copper landing used on the opposite side<br />

of the <strong>PCB</strong>. Surface mount pads do not have this layer.<br />

SOLDERMASK: This is the area you needs <strong>to</strong> be solder later. This value should be larger<br />

than the copper layer (begin layer) being used for the pad. The additional size is<br />

dependant on the <strong>PCB</strong> manufacturer and component specifications. We will use a 5 mil<br />

surround on all sides, this is done by increasing the radius or x-y dimensions.<br />

PASTEMASK: This is used <strong>to</strong> “paint” solder on<strong>to</strong> the board. This is used when the<br />

surface mount chips will be placed on a board and then the entire board is heated. This is<br />

generally 70 – 80% of the size of the copper layer is solder paste is being used.<br />

FILMMASK: Not used in this class.<br />

Parameters:<br />

Regular Pad: Size of the area around the hole


Thermal Relief: Used <strong>to</strong> insert space around the pad <strong>to</strong> ease thermal requirements during<br />

soldering. By using the menu in this column, you can select different predefined styles.<br />

For this project we will use a Flash geometry with the TR30_20 Flash Pattern.<br />

Anti Pad: Describes the spacing between a pad and a non-connected layer.<br />

Surface Mount Pad<br />

Through Hole Pad


For this tu<strong>to</strong>rial we will be using both surface mount and through hole components.<br />

Surface Mount<br />

In order <strong>to</strong> know the requirements for the landing pads for the components, the data sheet<br />

for the component must be consulted. The Layer Edi<strong>to</strong>r provides both <strong>to</strong>p and bot<strong>to</strong>m<br />

layers for the SOLDERMASK, PASTEMASK, and FILMMASK. Normally you will<br />

only define the TOP mask because that is the same side of the <strong>PCB</strong> as the BEGIN<br />

LAYER. Bot<strong>to</strong>m layers will be on the opposite side of the board and are not needed for<br />

most designs.<br />

We will construct a pad for the DS90LV049 component. This is a surface mounted<br />

LVDS Dual Line Driver with Dual Line Receiver. It uses rectangular landing pads. The<br />

last page of the data sheet contains the information required <strong>to</strong> make the pad:<br />

On the Parameters tab we set the units <strong>to</strong> millimeters and the decimal places <strong>to</strong> 2. We<br />

then begin defining the values of the Layers tab.<br />

The data sheet shows the pad as a 1.78 mm by .42 mm rectangle. We use this information<br />

<strong>to</strong> define the Regular Pad of the BEGIN LAYER. We leave the Thermal Relief and Anti<br />

Pad blank.<br />

Next we define the SOLDERMASK_TOP. The dimensions should be 5 mils larger width<br />

and height (on each side) than the BEGIN LAYER. That causes in each dimension have a<br />

+.254mm size. The result is a 2.04 mm by .68 mm.<br />

If this board was being manufactured for production, then we would specify a<br />

PASTEMASK. This should be smaller than the copper layer so we use 1.42 mm .34 mm.<br />

If the board is being soldered by hand, then the PASTEMASK is not required. For this<br />

tu<strong>to</strong>rial we will not use the FILMMASK.


Once that is complete, we use save the file using the Save As option in the file menu.<br />

Give the pad a descriptive name that you can use <strong>to</strong> identify it later.<br />

Through Hole<br />

The other style of pad is the through-hole pad. The most important thing for a through<br />

hole pad is <strong>to</strong> include the anti-pad. This is the space between non-connected parts layers<br />

of the board. From the parts list we constructed for this project we will use header pins as<br />

an example. This is a 3x1 square post. The pins are .025 inches (25 mils) square. This<br />

information is available on the product sheet. From the product sheet we also know that<br />

the pitch between holes is about 95 mils. To create the pad, we need a round hole that<br />

will fit the 25 mil square pin. Most manufacturers have a +/- 1 mils drill constraint.<br />

Therefore we need <strong>to</strong> size the drill larger than the 25 mil pin. Using math and looking at<br />

<strong>PCB</strong> manufacturer’s websites, we find that a hole size of 40 mils with a copper layer of<br />

57 mils will work.<br />

First use the Parameters tab <strong>to</strong> set the holes size <strong>to</strong> 40 mils, the Drill symbol <strong>to</strong> square and<br />

the size of the drill symbol <strong>to</strong> 40. On the Layer tab, TOPLAYER, DEFAULT INTERAL<br />

and BOTTOMLAYER should square 57 mils. The anti-pad for these layers is 75 mils.<br />

The last part <strong>to</strong> specify is the Thermal Relief for the pad. The thermal relief is used<br />

<strong>to</strong> reduce the copper connecting the pad <strong>to</strong> the layer or signal. The best way <strong>to</strong> do this is<br />

<strong>to</strong> select a style of anti-pad, the most common is Flash, then open the predefined styles<br />

and select one from the list. We will use TR30_20. The next step of making the pad for<br />

this is <strong>to</strong> define the SOLDERMASK. For this board we use 62 mils square for both <strong>to</strong>p<br />

and bot<strong>to</strong>m. The pad when finished will look similar <strong>to</strong> the following:


VIA<br />

A VIA is a connection between layers of the <strong>PCB</strong>. These are used <strong>to</strong> route power and<br />

signals where they are needed. The size of a VIA will depend on the specific use of that<br />

via. Normally for signals that do not carry current, you would want the smallest via<br />

possible. For power, you may want something larger. For this tu<strong>to</strong>rial we will use only<br />

one via, a round through hole via with a radius of 14 mils. The <strong>PCB</strong>express website has<br />

information about the copper pad and anti-pad.<br />

Predefined Components<br />

One of the components we are using in this tu<strong>to</strong>rial is the NMOS BSS138 transis<strong>to</strong>rs.<br />

This is a standard part that has a predefined footprint. You can see this because there is a<br />

JEDEC specified on the data sheet. The JEDEC for this part is SOT23. For this part we<br />

will not have <strong>to</strong> define the padstack or footprint.<br />

For the rest of the tu<strong>to</strong>rial you need <strong>to</strong> complete the pad stack for each of the components.<br />

One helpful feature is that only one padstack needs <strong>to</strong> be created for each component that<br />

has standard sizing. These components include resis<strong>to</strong>rs and capaci<strong>to</strong>rs. They are sized<br />

with information like 0402, 0603 etc. This allows many different 0603 parts <strong>to</strong> share the<br />

same padstack and footprint. They’re information is defined using a part table, we’ll<br />

discuss that later. It will not help for this tu<strong>to</strong>rial because we are using a different size for<br />

each component. Remember <strong>to</strong> save the pads in<strong>to</strong> the pad direc<strong>to</strong>ry of you base tu<strong>to</strong>rial<br />

direc<strong>to</strong>ry.


Footprint<br />

The next step in <strong>PCB</strong> design is <strong>to</strong> construct the foot print of each part that we will be<br />

using. This allows for the physical placement of the components and the mapping of pins<br />

from the foot print <strong>to</strong> the schematic we will make later. The footprint is created using the<br />

program called Allegro. This will create the Package Symbol. Once the footprint<br />

is created there will be two files for the foot print, .psm and .dra.<br />

For this part of the tu<strong>to</strong>rial we will complete the footprint for one component. It is the<br />

process for creating each footprint. We will design the footprint for the DS90LV049. The<br />

first step is <strong>to</strong> start-up Allegro Symbol Edi<strong>to</strong>r on the Library Management<br />

flow of the Project Manager. It will take a few seconds for the window <strong>to</strong> appear<br />

but it will open a blank page, or the last footprint that was worked on.<br />

To start the process we will use the Package Symbol Wizard. This is launch through the<br />

File, New menu and selecting the wizard option. It is important <strong>to</strong> give the component a<br />

name that you will be able <strong>to</strong> recognize later. Once you give it a name, you should also<br />

place it in the dra direc<strong>to</strong>ry that you created. This will help <strong>to</strong> organize your design.<br />

The Wizard<br />

The wizard will start by asking what type of package <strong>to</strong> create. This is important because<br />

it should match the package that you will be using later. The differences between the<br />

different packages are as follows.<br />

DIP (Dual Inline Package): This is a through-hole package that has a line of pins on both<br />

sides of the component.<br />

SOIC (Small Outline Integrated Circuit): This is a surface mount packages with pins on<br />

both sides of the package.


PLCC/QFP (Plastic Leaded Chip Carrier/Quad Flat Pack): The offer pings all around a<br />

device.<br />

PGA/BGA (Pin Grid Array/Ball Grid Array): These packages have pins that make<br />

contacts under a chip. Pin Grids are through hole while Ball Grids are surface mount.<br />

TH Discrete: These are through-hole discrete components.<br />

SMD Discrete: These are surface mounted discrete components.<br />

SIP (Single Inline Package): These are a row of pins in a straight line.<br />

ZIP: These packages are named because of the staggered pin arrangement that resembles<br />

a zipper.<br />

Each component will required the correct package type for creating the footprint. The<br />

driver and logic gate will require the SOIC, the resis<strong>to</strong>rs, capaci<strong>to</strong>rs and LED will require<br />

SMD Discrete and the header pins will require the SIP package. The parameters for each<br />

component are provided on the data sheet for the component. Now we will begin creating<br />

the footprint for the DS90LV049.<br />

The first step is choosing the package type, SOIC. The next screen allows you <strong>to</strong> choose a<br />

template for what the package will look like. We will choose the Default<br />

<strong>Cadence</strong> supplied template. It is important <strong>to</strong> press the Load Template<br />

but<strong>to</strong>n.<br />

The next screen describes the general parameters for the design. The units used <strong>to</strong> enter<br />

dimensions in this wizard should be the units used on the data sheet. That will make it


simple <strong>to</strong> create the part. The units used <strong>to</strong> create the package symbol are the units that<br />

are actually used <strong>to</strong> create the outline of the package. It is generally a good idea <strong>to</strong> keep<br />

these units the same. Because we have the dimensions for this part in millimeters we<br />

select millimeters for both options. The accuracy is how many decimal points will be<br />

used.<br />

The next screen is where the information for the package is entered. Using the diagram<br />

on the left of the window and the information on the data sheet, all the values can be<br />

entered. It is important <strong>to</strong> match the orientation of the symbol with the data sheet. For this<br />

part, the pins on the data sheet on are the <strong>to</strong>p and bot<strong>to</strong>m of the package while <strong>Cadence</strong><br />

defines them on the sides of the package. The following screen shot shows the parameters<br />

as entered for the DS90LV049.<br />

The next screen needs input for the padstack that is being defined. For these parts we use<br />

the pads we created earlier in the tu<strong>to</strong>rial. It also asks for the padstack <strong>to</strong> use for pin 1.<br />

This is often done <strong>to</strong> identify the pin 1 of a package so it is identifiable visually. It is not


equired but can be done. You could make a pad that is a different shape. We will not be<br />

doing that for this part. There are other ways <strong>to</strong> identify pin 1, and we will be doing that<br />

later.<br />

So we start by choosing the padstack for the symbol pins. Selecting the browse but<strong>to</strong>n<br />

will bring up the Padstack Browser. There are many <strong>Cadence</strong> included pads as well as the<br />

pads we created earlier. Find the pad you created earlier for the component, highlight it<br />

and press OK. It will then be entered in the Padstacks Window.<br />

Press next and it will take you <strong>to</strong> the Symbol Compilation screen. The first option is up <strong>to</strong><br />

you, I select pin 1 of symbol. The second option is <strong>to</strong> create the compiled symbol. You<br />

can choose <strong>to</strong> do that now or not. We will compile it again later so it does not matter what<br />

you choose.


The last window is a summary. Click finish and your footprint will be created.<br />

Any time a change is made <strong>to</strong> this file, it will need <strong>to</strong> be generated again. This is done<br />

from the file menu. Select File, Create Symbol. This will generate the .psm file.


Be sure <strong>to</strong> place it in you psm direc<strong>to</strong>ry, The symbol must be regenerated anytime you<br />

make a change <strong>to</strong> the dra file.<br />

Complete this process for all the components that you will be using. Remember that the<br />

standard components (resis<strong>to</strong>rs and capaci<strong>to</strong>rs) that use the same sizing only need one<br />

footprint for the same sized component. Also remember that the NMOS does not need<br />

you <strong>to</strong> define the footprint because it is already provided.<br />

Part Developer<br />

The next step in the board creation is creating schematic cells for each part. This allows<br />

for the schematics <strong>to</strong> be created. The first step is <strong>to</strong> change the license suite. This is done<br />

from the Project Manager, <strong>PCB</strong> Librarian Expert. Then start Part Developer from<br />

the Library Management flow. Once it is started up you will be presented with a<br />

simple screen:<br />

New Cell<br />

To create a new cell, go <strong>to</strong> File, New, Cell. Select the tu<strong>to</strong>rial library and name the cell<br />

that will be created. For this example we will continue with the LVDS driver/receiver,<br />

DS90LV049. It is important <strong>to</strong> remember that the cell is independent of the foot print we<br />

created earlier. It is a good idea however <strong>to</strong> make them similar.<br />

Package<br />

The cell now needs <strong>to</strong> be attached <strong>to</strong> the foot print that was created before. From the file<br />

menu select, New, Package. This will add a package <strong>to</strong> the hierarchy on the left and<br />

display the following screen, which is also available by clicking on the the component<br />

under the package menu:


There are some option boxes near the bot<strong>to</strong>m of the screen. This is where we need <strong>to</strong><br />

start. The Class is just a general description of what the part will do, for this we are<br />

choosing IC. The JEDEC Type is the important part. Here we select the footprint that we<br />

created in Allegro. It should appear in the list because we added the path <strong>to</strong> the psmpath<br />

earlier. Next we go <strong>to</strong> the Package Pin tab.<br />

The package pins will be mapped <strong>to</strong> the pins on the footprint. Pin operations are<br />

completed through the pin but<strong>to</strong>n near the <strong>to</strong>p of the tab. The first one we will do is add.<br />

This screen will be displayed.


There are two main types of pins used, Scalar and Vec<strong>to</strong>r. We will only be using<br />

scalar pins. The prefix box is name that will be displayed on the screen. Using the From<br />

and To boxes, you can add an arrays of pins <strong>to</strong> the package at one time. We will add<br />

names for all the pins we have in this package. The Type drop down box is used <strong>to</strong><br />

describe the pin <strong>to</strong> the program. The main types we will be using are input, output, power<br />

and ground. So we enter the appropriate information for a pin and then click the add<br />

but<strong>to</strong>n. We can add several pins at once without leaving this window. When we are<br />

finished we press the OK but<strong>to</strong>n and the pins are added <strong>to</strong> the package.


Once the pins are added the part developer window will look like:


Then using the S1 field in the Part Developer we assign the named schematic pins <strong>to</strong> the<br />

physical pins of the footprint. This is easily done by entering the pin number in the S1<br />

field of each row. This will add the pin assignments <strong>to</strong> the Physical Pin pane of the<br />

window. The result looks like:<br />

The next step is <strong>to</strong> generate the symbol and then save. Generating the symbol is easy<br />

done by clicking the Generate Symbol(s) but<strong>to</strong>n. This displays a Generate<br />

Symbol(s) dialog box, we will generate the symbol for the first functional group (S1)<br />

and this will be created new. We then save the package using File, Save. This process<br />

needs <strong>to</strong> be completed for XOR gate, header, LED, and transis<strong>to</strong>r.<br />

As mentioned before, the JEDEC type for the transis<strong>to</strong>r is SOT23. From the data sheet<br />

we know there are 3 terminals but we do not know how the pins map <strong>to</strong> each other. So we<br />

need <strong>to</strong> look at the foot print of the SOT23. Once we add the pins from the schematic <strong>to</strong><br />

the Functional Group of the package, the Footprints part of the hierarchy will be<br />

displayed. If you look at the general tab of the foot print it will show you the direc<strong>to</strong>ry of<br />

the footprint for the SOT23. Open the file in Allegro and see how the pin numbers are<br />

assigned.<br />

Part Table<br />

Components like resis<strong>to</strong>rs and capaci<strong>to</strong>rs have the same function but often with different<br />

values. The important differences are the value of the component and the size of the


footprint. Footprints can be reused between different components so that’s why we<br />

defined the standard ones earlier. We will now define the Part Table for resis<strong>to</strong>rs and<br />

capaci<strong>to</strong>rs. This could also be done for induc<strong>to</strong>rs, but we are not using them for this<br />

project.<br />

The first step is <strong>to</strong> start the part developer again. Again select File, New, Cell. This time<br />

we will call the cell RESISTOR.<br />

Next we create a new package. We do not need <strong>to</strong> specify a JEDEC type in the General<br />

tab. You will need <strong>to</strong> create 2 pins and generate the symbol. The next step is where we<br />

create the Part Table.<br />

Select the Part Table Files option in the hierarchy browser. Nothing will be<br />

displayed, which is okay. Right click on the name and select NEW. This will bring up the<br />

Ptf Edi<strong>to</strong>r. This is the Part Table File edi<strong>to</strong>r.<br />

Select the Header choice and there will be three sub tables in the right pane. The Key<br />

Properties table is the one we will be using first. The first line will be Value and<br />

place a ? mark in the value cell.. Next we will enter lines in<strong>to</strong> the Injected<br />

Properties table.Place the following entries in the table: PART_NUMBER, VALUE,


TOLERANCE, JEDEC_TYPE, COST, DESCRIPTION. If you think something else will<br />

be useful, then add it <strong>to</strong>o.<br />

We then start adding rows <strong>to</strong> the part table; this done by selecting the Part Rows and<br />

pressing the ADD but<strong>to</strong>n. This will insert a new line in<strong>to</strong> the table <strong>to</strong> be filled out. Enter<br />

the resis<strong>to</strong>r information that you have collected for this tu<strong>to</strong>rial. Then follow the same<br />

steps for the capaci<strong>to</strong>rs. The finished Part Rows will look like:


Complete this for the capaci<strong>to</strong>rs; all the parts should now be defined.<br />

Schematics<br />

The schematic is where first pieces of the overall design are put <strong>to</strong>gether. The symbols<br />

are used <strong>to</strong> make the logical connections between parts. To star up the schematic edi<strong>to</strong>rs<br />

you use the <strong>Design</strong> Entry <strong>to</strong>ols that starts up Concept-HDL. The window will<br />

start up with a blank schematic.


The first step is <strong>to</strong> add the components we will be using. This is done with the<br />

Component, Add and then selecting the Library we are taking the components<br />

from. For this tu<strong>to</strong>rial, the library is tu<strong>to</strong>rial_lib. Highlight the component you<br />

want <strong>to</strong> add, and then drag the mouse over the Concept window. The schematic should<br />

appear with the mouse. Click once <strong>to</strong> place the component in the schematic. Do this for<br />

each of the components we will be adding. Once all the components are added, press the<br />

close but<strong>to</strong>n on the Add Component window. Then, <strong>to</strong> end the component adding<br />

process, right click in the Concept window and select done.


In order <strong>to</strong> select the correct part for the resis<strong>to</strong>rs and capaci<strong>to</strong>rs we need <strong>to</strong> use the part<br />

table. Select the part that needs <strong>to</strong> be modified, right-click and select modify. The part<br />

Physical Part Filter window will appear.<br />

Select the correct line for each for and then press close. Do this for all resis<strong>to</strong>rs and<br />

capaci<strong>to</strong>rs. All components are now on the schematic. The final step of the schematic is<br />

<strong>to</strong> connect the parts with wires. The wire <strong>to</strong>ol can be found using the Wire menu at the<br />

<strong>to</strong>p of the screen. Thin wires will be used. To start creating the wires, select the Draw<br />

menu option.<br />

While there is no requirement for the schematic <strong>to</strong> look like the final layout of the<br />

physical components, it is a good idea <strong>to</strong> keep them close. It allows for an easy<br />

correspondence between the two. To start wiring the parts <strong>to</strong>gether, select the pin of one<br />

device, start routing the wire, move the mouse <strong>to</strong> another location and click. Each time


you click, a new point will be added <strong>to</strong> the path and the wire will retain the pattern it has.<br />

This allows for the wires <strong>to</strong> be routed easily even when dealing with complex designs.<br />

Explore the wiring <strong>to</strong>ol and wire the components <strong>to</strong>gether in the method of our original<br />

design. The capaci<strong>to</strong>rs are used as decoupling capaci<strong>to</strong>rs and should be wired as such.<br />

The final product will appear similar <strong>to</strong> this:<br />

Board Layout<br />

Laying out the board is the process of actually placing the components on the board that<br />

will be produced. Some of the key aspects <strong>to</strong> start this part are board size, component<br />

location and trace routing. Another important aspect of the board design is keeping it<br />

synchronized with the schematic. Keeping it synchronized allows for changes <strong>to</strong> be<br />

tracked and completed with out error.<br />

Creating a New Board<br />

To create a new board file, open the Board <strong>Design</strong> flow and choose Layout. This will<br />

launch the <strong>PCB</strong> Librarian Expert. It is a good idea <strong>to</strong> locate the following information<br />

before you being. This information will vary depending on the board manufacturer you<br />

choose. Choosing a manufacturer like <strong>PCB</strong>express we get the associated values:<br />

Minimum Line width – 7 mils (min)<br />

Minimum Line <strong>to</strong> Line spacing – 7 mils (min)<br />

Minimum Line <strong>to</strong> Pad spacing – 7 mils (min)


Minimum Pad <strong>to</strong> Pad spacing – 7 mils (min)<br />

Default VIA padstack – VIA18R13 (not dependant on manufacturer)<br />

Now that we have those values we can start up the layout edi<strong>to</strong>r. From the Board<br />

<strong>Design</strong> flow, choose Layout. This will bring up Allegro, the same <strong>to</strong>ol we used<br />

before. This time however we will create a new board file. Name the file and place it in a<br />

direc<strong>to</strong>ry that you will remember.<br />

This will bring up a blank design screen. The first step will be <strong>to</strong> place the board<br />

boundary. This defines the dimensions of the board. This is done by selecting the<br />

rectangle <strong>to</strong>ol. The pane on the right side of the window will display Active Class and<br />

Subclass. These define that kind of line or shape will be drawn. The first thing we will be<br />

doing is defining the Board Geometry. You can either free draw the shape or use the P<br />

key in the bot<strong>to</strong>m of the pane. This will place the courser is specific places around the<br />

grid. You will also need <strong>to</strong> define the Route Keepin and the Component Keepin.<br />

These are done the same way the Board Geometry is done, except they need <strong>to</strong> be 20 mils<br />

inside of the Board Geometry. This is a manufacturer specification that allows for small<br />

differences during manufacturing.


The next step is <strong>to</strong> synchronize the schematic with the board. This is done with the Board<br />

<strong>Design</strong> flow. Press the <strong>Design</strong> Sync but<strong>to</strong>n and select export physical. The follow<br />

screen will be displayed.<br />

The package option can be left on Preserve; the Regenerate Physical Net Names can also<br />

be left the way it is. The important part <strong>to</strong> change is the Input Board File and Output<br />

Board. Finally, the BackAnnotate Schematic should also be checked. The BackAnnotate<br />

option copies information back from the layout <strong>to</strong> the schematic keeping the information<br />

<strong>to</strong>gether. For the input and output files, select the board you just created. This should<br />

complete without errors if you completed the previous steps correctly. If you do receive<br />

an error, then look at the error log and attempt <strong>to</strong> fix it. If you want you may look at the<br />

log file. It is important <strong>to</strong> keep this files synchronized because it will allow you <strong>to</strong> find<br />

errors in routing.<br />

Quick Setup<br />

In order <strong>to</strong> efficiently layout the <strong>PCB</strong> there are a few things that should be setup. Once<br />

the board file is created open the Setup and choose Drawing Options. Then choose the<br />

Display tab and make sure the following options are selected.


Board Parameters<br />

Next we setup the number of layers used in the board and some of the criteria used. To<br />

set the number of layers in the board select Define Xsection but<strong>to</strong>n in the menu bar.


The screen that comes up will show the existing layers of the board. We will have 4<br />

layers of copper, so we need <strong>to</strong> insert 2 plane layers and 2 dielectric layers. The ground<br />

plane should be closets <strong>to</strong> the <strong>to</strong>p plane. Generally place a ground plane close <strong>to</strong> any<br />

plane with high speed signals. The bot<strong>to</strong>m layer will also be used for signaling, so we<br />

place the power (VCC) plane under between the ground and bot<strong>to</strong>m plane. The planes are<br />

also normally done as a Negative Film Type. If you were manufacturing this board, this<br />

is also the screen where you define the thickness of each layer. This is done by click on<br />

the arrow along the left for each layer and selecting the show property. Then enter the<br />

value. It will be saved when you move <strong>to</strong> another layer.<br />

If you do not have the Xsection but<strong>to</strong>n, you need <strong>to</strong> change license suites <strong>to</strong> <strong>PCB</strong> <strong>Design</strong><br />

Expert.


Placing Components<br />

The next thing <strong>to</strong> do is <strong>to</strong> begin placing components. This is done through the Place<br />

menu. Select Manually, and then and expand the Components by refdes. This<br />

will show the components that exist in the schematic. Begin placing them roughly where<br />

they will go, you can move them later using the Edit menu.<br />

A very rough placement of all the components would look like the following:


Notice the lines connecting different shapes. This is called a rats nest because it<br />

shows where some connections need <strong>to</strong> be made. The first thing <strong>to</strong> do is <strong>to</strong> make a better<br />

arrangement of the components. Place them physically where they should go.<br />

The final configuration will be required <strong>to</strong> have all the pieces inside of the Board<br />

Geometry.


Once you have arranged the pieces in a good pattern, it would be time <strong>to</strong> start wiring. We<br />

will first mirror a component <strong>to</strong> get practice with that. Mirror a component does not just<br />

rotate it 180 degrees, but also moves it <strong>to</strong> the back side of the board. This allows<br />

components <strong>to</strong> be placed on the underside of the <strong>PCB</strong>. The first step is <strong>to</strong> select mirror<br />

from the Edit menu. We will be mirroring the XOR gate for this demo because it uses the<br />

low speed CMOS signals. Keeping the differential signals on <strong>to</strong>p is important because it<br />

has the ground plane <strong>to</strong> insulate it.<br />

Wiring<br />

Now that the components have been placed where we think they should go, it is time <strong>to</strong><br />

start wiring. We are going <strong>to</strong> use differential lines <strong>to</strong> connect the SMA connec<strong>to</strong>rs <strong>to</strong> the<br />

LVDS Driver and Receiver. This is done <strong>to</strong> preserve the signal integrity. The first step is<br />

<strong>to</strong> define the differential pair. This is done through the Logic menu at the <strong>to</strong>p of the page.<br />

Select the Assign Differential Pairs option. The Screen that appears is where you will<br />

define what signals will be differential. Differential pairs should be wired manually <strong>to</strong><br />

provide the best signal integrity.<br />

Select the differential signals, assign them a name and press the Add but<strong>to</strong>n. Do this for 3<br />

pairs used in this design. Then click OK. The next step is in the setup menu. Select the<br />

Constraints option. This will bring up the following window.


For now we will just be editing the Electrical constraint sets. This will allow<br />

us <strong>to</strong> define the style of the differential pair. The window will display with several tabs in<br />

the middle. Select the Assign tab and add the differential pairs you created the<br />

Assigned Objects box. Next select the DiffPair Values tab open the Calcula<strong>to</strong>r.<br />

This will help you decide the parameters for the differential pair. If we use calcula<strong>to</strong>r <strong>to</strong><br />

specify a differential impedance of 100 ohms and a gap of 7 mils, then it will calculate<br />

the line width. The impedance should be 100 ohms because that’s what the LVDS lines<br />

are setup for and the line gap is set <strong>to</strong> 7 because that is the minimum spacing. Change the<br />

values in the calcula<strong>to</strong>r and see what else you can get.


Close out of this menu and we can place the differential signals. The signals will be<br />

routed like any other signal.<br />

Power Planes<br />

The power for this and most <strong>PCB</strong> is distributed on a plane. These are entire layers of the<br />

<strong>PCB</strong> that are conductive. For this Board we have one power and one ground plane. To set<br />

up the plane we draw an etch rectangle for the proper layer and assign it the correct net<br />

name. The steps for this are as follows: Select the Shape menu, and the Rectangular<br />

option. One the right hand side of the screen, set the class <strong>to</strong> Etch and the subclass <strong>to</strong> the<br />

layer you want <strong>to</strong> draw on. Next, assign a net name using the options dialog box. Then<br />

draw the plane over the area of the board, stay inside of the keep-in.


Manual Signal Routing<br />

Manual signal routing should be done anytime there are important signals <strong>to</strong> be routed. It<br />

is also a good idea <strong>to</strong> route power by hand. Some people prefer <strong>to</strong> route everything by<br />

hand. There are other methods though, but manual routing is a required skill <strong>to</strong> have. A<br />

good idea is <strong>to</strong> save a copy of the layout without any routing done. This allows for<br />

moving pieces around later without needing <strong>to</strong> remove a large number of traces.<br />

Trace<br />

First select the connect option from the Route menu. Next select the pin of component<br />

you wish <strong>to</strong> start routing. As you move the mouse, the path will be drawn. You can set<br />

way-points with the mouse by click on specific spots. When you reach the destination<br />

just click on end point and the trace is complete. The same method is used <strong>to</strong> route<br />

differential pairs.


Via<br />

When routing manually, there will often be times when you need <strong>to</strong> route between layers.<br />

This is done by using a via. We must add the vias <strong>to</strong> the design. From the Setup menu<br />

select the Vias submenu; then select Au<strong>to</strong>define B/B Via. The follow screen will<br />

be displayed.


On this screen we will add the via we created. Open the Input Pad Name option box<br />

and select the via that was created earlier. Press the Generate but<strong>to</strong>n in the bot<strong>to</strong>m left<br />

corner. And then select DEFAULT <strong>to</strong> move the list from the Available <strong>to</strong> Selected<br />

Box. This will allow the vias <strong>to</strong> be used later <strong>to</strong> define signal routing between layers.<br />

To add a via when wiring, the steps are straight forward. In the right pane of the layout<br />

edi<strong>to</strong>r, you will be able <strong>to</strong> configure the pad you want <strong>to</strong> use. 1) Begin wiring at the<br />

starting point of the trace. 2) Next draw a line <strong>to</strong> where you want the via <strong>to</strong> be placed. 3)<br />

Click once <strong>to</strong> set a point. 4) In the Option tab select the via you want <strong>to</strong> use. 5) Click on<br />

the spot you want the via. 6) Continue wiring or click again <strong>to</strong> end the trace. When<br />

finished you will have a properly connected via and traces.


Wire the power and grounds. Be mindful of leaving space for routing signals in the<br />

future. The following is a capture of this design with power, ground and differential<br />

signals routed.


Au<strong>to</strong>matic Routing<br />

There are two au<strong>to</strong>-routing <strong>to</strong>ols included in this distribution of cadence. For this tu<strong>to</strong>rial<br />

we will briefly cover the SPECCTRA au<strong>to</strong>-routing <strong>to</strong>ol. Au<strong>to</strong>-routing, as the name<br />

implies, is a <strong>to</strong>ol that will route the signals using a set of calculations. It follows a set of<br />

parameters that are provided by the user. The initial board boundary and keepin that was<br />

defined are used by the au<strong>to</strong>-router.


Start SPECCTRA by using the Route, SPECCTRA routing menu options. You may<br />

get an error message, ignore it for now. Once the <strong>to</strong>ol opens, you will see there are many<br />

options. The first one we must use is in the Select menu and choose Vias for<br />

Routing and then By List.This will display a list of available vias. Select the vias<br />

you want the au<strong>to</strong>-router <strong>to</strong> use.


Next we use the Au<strong>to</strong>route menu and choose route. The following screen has a few more<br />

options. We will leave the default options. The options should be straight forward. Via<br />

and Pin Sharing allow for the nets <strong>to</strong> be routed through the same via or pin.<br />

Then press OK and the au<strong>to</strong>-router should route the signals. The screen may flash as it<br />

iterates through different combinations. Eventually it will converge on a completed<br />

layout. You may receive errors. One if your design is very complex and the au<strong>to</strong>-router<br />

converges <strong>to</strong>o slowly and will give up. The other is if the design is <strong>to</strong>o simple, and the<br />

au<strong>to</strong>-router suggests you simply the design. You can see the results in the window. You<br />

can now exit the au<strong>to</strong>-router. This is accomplished through the File menu, Quit<br />

option. Here you can choose <strong>to</strong> save and quit or quit with out saving.


Completed <strong>Design</strong><br />

The design and layout of the <strong>PCB</strong> is now completed. There many more options <strong>to</strong><br />

explore, if all the options were explained this tu<strong>to</strong>rial would fill several books. An<br />

important step not covered through this point in the tu<strong>to</strong>rial was the Silk Screen layer of<br />

the board. The silk screen allows for shapes and symbols <strong>to</strong> be written on<strong>to</strong> the <strong>to</strong>p and or<br />

bot<strong>to</strong>m of the board. There is an appendix describing how this should be done.


Setting-up Layout Colors<br />

To increase the usability of the layout edi<strong>to</strong>r, it is possible <strong>to</strong> assign different colors <strong>to</strong> the<br />

different layers. This will allow you <strong>to</strong> quickly identify what is connected. First select the<br />

colors palette by click the but<strong>to</strong>n with 4 colored squares.<br />

Then you can start changing the colors of each layer. I recommend using a different color<br />

for each layer. The colors you choose are up <strong>to</strong> you. Here is a copy of the colors I used.

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