MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Secondary Cache Interface 69
4-Word Read Sequence
Cycle
SCClk
SC[A,B]Addr(18:0) Adr0
SCTagLSBAddr
SC[A,B]DWay
SCData(127:0)
SCDataChk(9:0)
SC[A,B]DOE*
SC[A,B]DWr*
SC[A,B]DCS*
SCTWay
SCTag(25:0)
SCTagChk(6:0)
SCTOE*
SCTWr*
SCTCS*
A 4-word read sequence is performed by a CACHE Index Load Data (S)
instruction to read a doubleword of data and 10 check bits from the secondary
cache data array.
Figure 5-3 depicts a secondary cache 4-word read sequence. A quadword is read
from the index specified by PA(23:6), and the way specified by VA(0) of the
CACHE instruction.
The doubleword specified by VA(3) is then stored into the CP0 TagHi and TagLo
registers, and the corresponding check bits are stored into the CP0 ECC(9:0)
register. The data may be examined by copying the CP0 TagHi, TagLo, and ECC
registers to the general registers with the MTC0 instruction.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
X
Figure 5-3 4-Word Read Sequence
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
DatX0