MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Secondary Cache Interface 61
5.2 Secondary Cache Interface Frequencies
Errata
The secondary cache interface operates at the frequency of SCClk, which is
derived from PClk. The SCClkDiv mode bits select a PClk to SCClk divisor of 1,
1.5, 2, 2.5, or 3, using the formula described in Chapter 7, the section titled
“Secondary Cache Clock.”
Synchronization between the PClk and SCClk is performed internally and is
invisible to the system. The processor supplies six complementary copies of the
secondary cache clock on SCClk(5:0) and SCClk(5:0)*.
The outputs and inputs at this interface are triggered by an internal SCClk. The
relationship between the internal SCClk and the external SCClk[5:0]/SCClk[5:0]*
can be programmed during boot time by setting the SCClkTap mode bits (see the
section titled “Mode Bits” in Chapter 8 for detail on mode bits).
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997