MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

52 Chapter 4.
Read hit
Intervention shared hit
Read miss obtained Shared
CACHE Index Store Tag (S)
Legend:
Internally initiated action:
Externally initiated action:
(S) Secondary cache
A secondary cache block can be changed from one state to another as a result of
any of the following events:
• primary cache read/write miss
• primary cache write hit to a Shared or CleanExclusive block
• secondary cache read miss
• secondary cache write hit to a Shared or CleanExclusive block
• a CACHE instruction
• external intervention shared request
• intervention exclusive request
• invalidate request
These events are illustrated in Figure 4-7, which shows the secondary cache state
diagram.
CACHE Index WriteBack Invalidate (S)
CACHE Index Store Tag (S)
CACHE Hit Invalidate (S)
CACHE Hit WriteBack Invalidate (S)
Invalid
Intervention exclusive hit
Invalidate hit
Shared
Intervention shared hit
Intervention shared hit
Write hit and Upgrade ACK
Clean
Exclusive
Dirty
Exclusive
Figure 4-7 Secondary Cache State Diagram
Read hit
Read hit
Write hit
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
Write hit
Read miss obtained CleanExclusive
CACHE Index Store Tag (S)
Write miss
Read miss obtained DirtyExclusive
CACHE Index Store Tag (S)