MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

viii Table of Contents
1
Introduction to the R10000 Processor
MIPS Instruction Set Architecture (ISA) .....................................................................................2
What is a Superscalar Processor?.................................................................................................3
Pipeline and Superpipeline Architecture..........................................................................3
Superscalar Architecture .....................................................................................................3
What is an R10000 Microprocessor? ............................................................................................4
R10000 Superscalar Pipeline ...............................................................................................5
Instruction Queues...............................................................................................................6
Execution Pipelines ..............................................................................................................6
64-bit Integer ALU Pipeline......................................................................................6
Load/Store Pipeline...................................................................................................7
64-bit Floating-Point Pipeline...................................................................................7
Functional Units ...................................................................................................................9
Primary Instruction Cache (I-cache)..................................................................................9
Primary Data Cache (D-cache) ...........................................................................................9
Instruction Decode And Rename Unit..............................................................................10
Branch Unit ...........................................................................................................................10
External Interfaces................................................................................................................10
Instruction Queues.........................................................................................................................11
Integer Queue .......................................................................................................................11
Floating-Point Queue...........................................................................................................11
Address Queue .....................................................................................................................12
Program Order and Dependencies ..............................................................................................13
Instruction Dependencies....................................................................................................13
Execution Order and Stalling .............................................................................................13
Branch Prediction and Speculative Execution .................................................................14
Resolving Operand Dependencies.....................................................................................14
Resolving Exception Dependencies...................................................................................15
Strong Ordering....................................................................................................................15
An Example of Strong Ordering ..............................................................................16
R10000 Pipelines .............................................................................................................................17
Stage 1 ....................................................................................................................................17
Stage 2 ....................................................................................................................................17
Stage 3 ....................................................................................................................................18
Stages 4-6 ...............................................................................................................................18
Floating-Point Multiplier (3-stage Pipeline)...........................................................18
Floating-Point Divide and Square-Root Units .......................................................18
Floating-Point Adder (3-stage Pipeline) .................................................................18
Integer ALU1 (1-stage Pipeline)...............................................................................18
Integer ALU2 (1-stage Pipeline)...............................................................................18
Address Calculation and Translation in the TLB ..................................................19
Implications of R10000 Microarchitecture on Software............................................................20
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual