MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Cache Organization and Coherency 47
An instruction cache block can be changed from one state to the other as a result
of any one of the following events:
• a primary instruction cache read miss
• subset property enforcement
• any of various CACHE instructions
• external intervention exclusive and invalidate requests
These events are illustrated in Figure 4-2, which shows the primary instruction
cache state diagram.
Subset enforcement
CACHE Index Invalidate (I)
CACHE Index Store Tag (I)
CACHE Hit Invalidate (I, S)
CACHE Index WriteBack Invalidate (S)
Invalid
Legend:
Internally initiated action:
Externally initiated action:
(I) Instruction cache
(S) Secondary cache
Intervention exclusive hit
Invalidate hit
Figure 4-2 Primary Instruction Cache State Diagram
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
Valid
Read miss
CACHE Index Store Tag (I)
Read hit