MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Interface Signal Descriptions 43
3.4 Test Interface Signals
Errata
JTDI
JTDO
JTCK
JTMS
TCA
TCB
Table 3-4 presents the R10000 processor test interface signals.
PLLDis and SelDVCO signal descriptions are revised in Table 3-4.
Table 3-4 Test Interface SignalsPLLDis
Signal Name Description
JTAG Signals
Type
PLLDis
JTAG serial data input
Serial data input.
JTAG serial data output
Serial data output.
JTAG clock
Clock input.
JTAG mode select
Mode select input.
Miscellaneous Test Signals
Testability control A (for manufacturing test only)
This signal must be tied to Vss, through a 100 ohm resistor.
Testability control B (for manufacturing test only)
This signal must be tied to Vss, through a 100 ohm resistor.
PLL disable (for manufacturing test only)
This signal must be tied to Vss through a 100 ohm resistor.
PLLRC
PLL Control Node (for manufacturing test only)
There must be no connection made to this signal.
PLLSpare(1:4) These four pins must be tied to Vss.
Spare(1,3) These two pins must be tied to Vss, through a 100 ohm resistor.
TriState
SelDVCO
Tristate Control
The system asserts this signal to tristate all outputs and input/
output pads except for SCClk, SCCLK*, and JTDO.
Select differential VCO (for manufacturing test only)
This signal must be tied to Vcc.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
Input
Output
Input
Input
Input
Input
Input
Input
Input