MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

20 Chapter 1.
1.7 Implications of R10000 Microarchitecture on Software
Superscalar Instruction Issue
The R10000 processor implements the MIPS architecture by using the following
techniques to improve throughput:
• superscalar instruction issue
• speculative execution
• non-blocking caches
These microarchitectural techniques have special implications for compilation and
code scheduling.
The R10000 processor has parallel functional units, allowing up to four
instructions to be fetched and up to five instructions to be issued or completed
each cycle. An ideal code stream would match the fetch bandwidth of the
processor with a mix of independent instructions to keep the functional units as
busy as possible.
To create this ideal mix, every cycle the hardware would select one instruction
from each of the columns below. (Floating-point divide, floating-point square
root, integer multiply and integer divide cannot be started on each cycle.) The
processor can look ahead in the code, so the mix should be kept close to the ideal
described below.
Column A Column B Column C Column D Column E
FPadd FP mul FPload add/sub add/sub
FPdiv FPstore shift mul
FPsqrt load branch div
store logical logical
Data dependencies are detected in hardware, but limit the degree of parallelism
that can be achieved. Compilers can intermix instructions from independent code
streams.
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual