MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Index I-15
SysAD[20:16]
interrupt register 105
SysAD[39:0]
during address cycle 103
SysAD[56:40]
during address cycle 103
SysAD[57]
secondary cache block way indication 103
SysAD[59:58]
uncached attribute 102
SysAD[63:0]
address cycle encoding 102
data cycle encoding 104
SysAD[63:60]
address cycle 102
interrupt 105
SysADChk, bus 182
SysADChk, signal 42, 164
SysClk cycle 93, 127, 148
SysClk, signal 28, 41, 80, 104, 106, 108, 109, 113,
121, 125, 154, 155, 215, 216, 366, 367
SysClkDiv, mode bits 156, 160, 165
SysClkRet, signal 41, 156, 158
SysCmd, bus 41, 95, 170, 181, 182
SysCmd[0] 90
ECC 100
processor data cycles 100
SysCmd[10:8] 95
data response 99
external intervention and invalidate requests 98
SysCmd[11:0]
map 101
protocol 107
SysCmd[11] 95
SysCmd[2:0]
processor write requests 98
SysCmd[2:1]
block data response 100
processor requests 97
SysCmd[4:3]
data cycles 100
external special requests 99
processor read requests 96
processor upgrade requests 97
SysCmd[5]
data cycles 99
SysCmd[5], bit 90
SysCmd[7:5]
external requests 98
processor requests 96
SysCmdPar, signal 41, 181
SysCorErr, signal 42, 168, 177, 179, 182
SysCyc, signal 42, 154
SysGblPerf, signal 28, 42, 56, 148
SysGnt, signal 41, 108, 109, 110, 112, 114, 116, 118,
120, 122, 124, 127, 132, 133, 134, 135,
136, 139, 148, 160, 162, 163, 336, 337,
361, 362
SysNMI, signal 42, 106, 339
SysRdRdy, signal 41, 109, 113, 115, 121, 125
and flow control 93
SysRel, signal 41, 108, 110, 112, 114, 116, 118, 120,
122, 124, 127, 132, 133, 134, 135, 136,
139, 148
SysReq, signal 41, 108, 109, 112, 114, 116, 118, 120,
122, 124, 139, 148, 162
SysReset, signal 42, 160, 162, 163, 204, 216, 336,
337, 338, 361, 362
SysResp, bus 42, 95, 105, 184
SysResp[4:0]
external completion response 130
SysResp[4:2]
driving completion indication 105
SysRespPar, signal 42, 184
SysRespVal, signal 42, 130, 160, 162, 163, 184
SysState, bus 42, 95, 104, 170, 184
SysState[0]
processor coherency data response 146
SysState[2:0]
encoding 104
SysStatePar, signal 42, 184
SysStateVal, signal 42, 104
System Call exception 349
system configuration
multiprocessor 35
uniprocessor 34
System interface 10, 79
arbitration
in a cluster bus system 82, 111
in a uniprocessor system 110
protocol 108
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997