MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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I- 12 Index PrcReqMax, mode bits 93, 113, 115, 121, 125, 164 precise exceptions 15 prediction, branch 374 prediction, secondary cache, way 63 prefetch instruction 25 primary data cache, see also cache, primary data 9 primary instruction cache, see also cache, primary instruction 9 Probe TLB for Matching Entry, instruction 285 processor block read request protocol 113 processor block write request 94 protocol 117 processor coherency data response 94 protocol 139 processor coherency state response protocol 138 processor double/single/partial-word read request protocol 115 processor double/single/partial-word write request protocol 119 processor eliminate request protocol 123 processor request 80, 86 flow control protocol 125 protocol 112 processor response 80, 87 protocols 137 Processor Revision Identifier (PRId) register 255 processor upgrade request 131 protocol 121 processor-specific instructions 26 program order 13 dynamic execution 13 instruction completion 371 instruction decoding 371 instruction execution 371 instruction fetching 371 instruction graduation 371 instruction issue 371 protection ECC 173 memory 328 parity 173 SECDED 173 sparse encoding 173 protocol arbitration, System interface 108 error handling 185 write back 45 write invalidate cache coherency 45 PTE (page table entry) 241 PTEBase, field 241, 259 Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual Q queue address 6 instruction 17 integer 6 R R, (region) field 245, 259 R, bit 258 R10000 processor ANDES architecture 4 caches 4 execution pipelines 6 overview 4 pipeline stages 5 superscalar pipeline 5 R4000 superpipeline 3 Random entries 243 Random register 238 RE, (reverse endian) bit 247 Read Indexed TLB Entry, instruction 285 read port, FPU 302 read sequences 68 16-word 71 32-word 71 4-word 69 8-word 70 tag 72 reference voltage 217 DC 212 register BadVAddr 241, 244, 259, 340 boundary scan, JTAG 206 bypass, JTAG 205 CacheErr 171, 172, 174, 175, 274 Cause 105, 106, 244, 252, 254 Compare 106, 244 Config 256 Context 241, 259 Count 106, 244
Index I-13 CP0 (description of) 235 dependency 14, 375 Diagnostic 261 ECC 69, 74, 273 EntryHi 245 EntryLo0 239 EntryLo1 239 EPC 254 Error Exception Program Counter (ErrorEPC) 284 Exception Program Counter (EPC) 254 file FPU 302 ports 375 FrameMask 240, 260 Index 237 instruction, JTAG 205 LLAddr 257 logical, see also physical register 17, 375 PageMask 242, 328 Performance Counter 264 permanent 372 physical, see also logical register 17, 375 Processor Revision Identifier (PRId) 255 Random 238 renaming 14, 372 Status 171, 172 ERL bit 316 EXL bit 316 SX bit 326 TS bit 330 USL field 316 UX bit 326 TagHi 69, 74, 278 TagLo 69, 74, 278 temporary 372 unnamed 373 WatchHi 258 WatchLo 258 Wired 238, 243 write before reading (necessity for) 160 XContext 259 renaming, register 372 repeat rate 29 accessing secondary cache 31 definition of 370 FPU 301 replacement algorithm, cache 9 request cycle 80 request number 87 freeing with completion response 130 request, outstanding 87 Reserved Instruction exception 351 reset cold 159, 162 power-on 159, 160 soft (warm) 159, 163 response bus signals 42 response cycle 80 revision number, R10000 processor 255 RM, field (FP) 311 RN, field (FP) 311 rounding modes, in FSR 311 RP, (reduced power) bit 247 RP, field (FP) 311 rules, arbitration for System interface 109 RZ, field (FP) 311 S SB, (secondary cache block size) bit 256 SC instruction 27 SC(A,B)Addr, signals 39, 62, 63 SC(A,B)DWay, signals 39, 62, 70, 75 SC, bit 256 SCADCS, signal 39 SCADOE, signal 39 SCADWr, signal 39 SCBDCS, signal 39 SCBDOE, signal 39 SCBDWr, signal 39 SCBlkSize, mode bits 51, 60, 92, 165 SCClk frequency 118, 139 SCClk, signal 39, 61, 157 SCClkDiv, mode bits 61, 156, 160, 165 SCClkTap, mode bits 157, 166 SCCorEn, mode bits 165, 177, 179 SCData, signal 39 SCDataChk, bus 176, 179 SCDataChk, signal 39 scheduling, dynamic 371 SCSize, mode bits 51, 60, 165 SCTag, signals 40, 66 MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Coprocessor 0 273 14.21 ECC Registe
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Coprocessor 0 275 CacheErr Register
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Coprocessor 0 277 CacheErr Register
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Coprocessor 0 279 Errata Primary In
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Coprocessor 0 281 Errata Errata Sec
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Coprocessor 0 283 Primary Data Cach
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Coprocessor 0 285 14.25 CP0 Instruc
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Coprocessor 0 287 14.27 CACHE Instr
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Coprocessor 0 289 Cache CACHE (cont
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Coprocessor 0 291 14.29 DMTC0 Instr
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Coprocessor 0 293 14.31 MFC0 Instru
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Coprocessor 0 295 MTPS 31 Format: M
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Coprocessor 0 297 14.34 TLBP Instru
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Coprocessor 0 299 14.36 TLBWI Instr
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15. Floating-Point Unit This sectio
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Floating-Point Unit 303 15.2 Floati
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Floating-Point Unit 305 Load and St
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Floating-Point Unit 307 63 63 Doubl
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Floating-Point Unit 309 Floating-Po
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Floating-Point Unit 311 Loading the
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Floating-Point Unit 313 Moves and C
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16. Memory Management This section
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Memory Management 317 Addressing Mo
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Memory Management 319 32-bit User M
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Memory Management 321 32-bit Superv
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Memory Management 323 32-bit Kernel
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Memory Management 325 0X BFFFFFFF 0
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Memory Management 327 64-bit Virtua
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Memory Management 329 Using the TLB
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17. CPU Exceptions This chapter des
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CPU Exceptions 333 17.3 TLB Refill
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CPU Exceptions 335 Priority of Exce
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Page 399 and 400: A. Glossary The following terms are
Page 401 and 402: A.6 Dynamic Scheduling The R10000 p
Page 403 and 404: A.11 Nonblocking Loads and Stores M
Page 405 and 406: A.13 Logical and Physical Registers
Page 407 and 408: Index I-1 Index Numerics 16-word, c
Page 409 and 410: Index I-3 uncached accelerated, des
Page 411 and 412: Index I-5 branch on CP0 instruction
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Page 415 and 416: Index I-9 TLBWR 285, 300 unsupporte
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Page 421 and 422: Index I-15 SysAD[20:16] interrupt r
Page 423 and 424: Index I-17 SysWrRdy, signal 41, 118
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