MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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I- 10 Index kuseg space 323 KX, bit 248, 316 L latency 29 accessing secondary cache 31 definition of 370 external coherency request 146 FPU 301 least-recently used replacement algorithm (LRU) 9 level sensing, input 212 list, free 372 LL instruction 27 LLAddr register 257 load hazards, CP0 285 load linked 27 load operations, FPU registers 305 Load/Store Unit pipeline 6 loads nonblocking 373 logic diagram, FPU 302 logical register initialization (necessity for) 160 logical register, see also physical register 375 LRU (least-recently used) replacement algorithm 9 M mapped, virtual address region 317 mapping table 375 Mask, field 242 master state 81 and flow control 93 matches, multiple, in TLB 330 MemEnd, mode bits 165 memory dependencies 14 memory ordering 15 memory protection 328 MFC0, instruction 286, 293 MIPS III ISA, disabled and enabled 240 MIPS IV, instruction set see also ISA 356 miscellaneous system signals 42 mispredicted branch 31 mode addressing 317 addressing, encodings 317 Kernel mode 317 Supervisor mode 317 User mode 317 operating 316 mode bits 164 CohPrcReqTar 102, 149, 152, 164 CTM 166, 361, 362 DevNum 164 Kseg0CA 164 MemEnd 165 ODrainSys 166, 212 PrcElmReq 123, 153, 164, 198 PrcReqMax 93, 113, 115, 121, 125, 164 SCBlkSize 51, 60, 92, 165 SCClkDiv 61, 156, 160, 165 SCClkTap 157, 166 SCCorEn 165, 177, 179 SCSize 51, 60, 165 SysClkDiv 80, 156, 160, 165 mode definitions, DC 212 Move from CP0, instruction 285 Move from performance counter, instruction 295 Move from performance event specifier, instruction 295 move instruction (FP) 313 Move to CP0, instruction 285 Move to performance counter, instruction 295 Move to performance event specifier, instruction 295 Move To/From the Performance Counter, instructions 294 MP, field 261 MTC0, instruction 69, 286, 296 multiple matches, in TLB 330 multiplier pipeline 6 multiply unit, FPU 301 multiprocessor system 35 arbitration 111 cluster bus 35 with external agent 35 multiprocessor system, using dedicated external agents 84 multiprocessor system, using the cluster bus 85 N NACK completion response 130 NACK, signal 90 Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
Index I-11 NMI see also nonmaskable interrupt 284 NMI, bit 249, 250 nonblocking cache 25 nonblocking, loads and stores 373 Nonmaskable Interrupt (NMI) exception 106, 332, 339 normal read, cache test mode 366 normal write, cache test mode 364 NT compatibility, LLAddr register 257 number, request 87 O ODrainSys, mode bit 166, 212 offset, in page address 328 op field encoding of CACHE instructions 191 operating conditions, AC 215 operating mode Kernel 316, 322 Supervisor 316, 320 User 316, 318 operations, FPU 302 ordering, memory 15 ordering, strong 15 out of program order, execution 370 outgoing buffer 89, 91, 92 outstanding requests 87 overflow (FP) 310 P package configuration 219 package, see CLGA PAddr0, field 258 PAddr1, field 258 page address 328 offset 328 size code 328 defined 328 virtual 328 page table entry (PTE) array 241 PageMask register 242, 328, 329 parity protection 173 PClk, signal 61, 80, 366, 367 PE, bit 256 performance branch prediction 31 cache 31 R10000 28, 31 Performance Counter interrupt 244 Performance Counter register 264 permanent register 372 PFN bits 240 fields, in EntryLo registers 240 phase-locked loop 158 physical address 187, 188 physical memory addresses 328 physical page frame number 239 physical register, see also logical register 375 PIdx, primary cache index 67 pipeline 17 definition of 370 fetch 6, 17 floating-point 7 floating-point multiplier 6 integer ALU 6 latency 370 Load/Store Unit 6 out of order execution 370 repeat rate 370 sequence 370 stage (definition) 370 stage 1 17, 18 stage 2 17 stages 4-6 18 stalls 13 PLL 158 PLLDis, signal 43, 213 PLLRC, capacitor 221 PLLSpare, signals 213 PM, field 256 power interface signals, see also individual signals 38 power supply levels, DC 210 regulation 217 power-on reset 159 sequence 160 PrcElmReq, mode bit 123, 153, 164, 198 MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Coprocessor 0 273 14.21 ECC Registe
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Coprocessor 0 275 CacheErr Register
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Coprocessor 0 277 CacheErr Register
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Coprocessor 0 279 Errata Primary In
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Coprocessor 0 281 Errata Errata Sec
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Coprocessor 0 283 Primary Data Cach
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Coprocessor 0 285 14.25 CP0 Instruc
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Coprocessor 0 287 14.27 CACHE Instr
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Coprocessor 0 289 Cache CACHE (cont
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Coprocessor 0 291 14.29 DMTC0 Instr
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Coprocessor 0 293 14.31 MFC0 Instru
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Coprocessor 0 295 MTPS 31 Format: M
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Coprocessor 0 297 14.34 TLBP Instru
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Coprocessor 0 299 14.36 TLBWI Instr
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15. Floating-Point Unit This sectio
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Floating-Point Unit 303 15.2 Floati
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Floating-Point Unit 305 Load and St
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Floating-Point Unit 307 63 63 Doubl
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Floating-Point Unit 309 Floating-Po
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Floating-Point Unit 311 Loading the
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Floating-Point Unit 313 Moves and C
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16. Memory Management This section
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Memory Management 317 Addressing Mo
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Memory Management 319 32-bit User M
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Memory Management 321 32-bit Superv
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Memory Management 323 32-bit Kernel
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Memory Management 325 0X BFFFFFFF 0
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Memory Management 327 64-bit Virtua
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Memory Management 329 Using the TLB
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17. CPU Exceptions This chapter des
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CPU Exceptions 333 17.3 TLB Refill
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Page 373 and 374: CPU Exceptions 343 TLB Invalid Exce
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Page 387 and 388: CPU Exceptions 357 17.5 COP0 Instru
Page 389 and 390: 18. Cache Test Mode The R10000 proc
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Page 395 and 396: Cache Test Mode 365 Auto-Increment
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Page 399 and 400: A. Glossary The following terms are
Page 401 and 402: A.6 Dynamic Scheduling The R10000 p
Page 403 and 404: A.11 Nonblocking Loads and Stores M
Page 405 and 406: A.13 Logical and Physical Registers
Page 407 and 408: Index I-1 Index Numerics 16-word, c
Page 409 and 410: Index I-3 uncached accelerated, des
Page 411 and 412: Index I-5 branch on CP0 instruction
Page 413 and 414: Index I-7 F fetch pipeline 6, 17 fe
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Page 419 and 420: Index I-13 CP0 (description of) 235
Page 421 and 422: Index I-15 SysAD[20:16] interrupt r
Page 423 and 424: Index I-17 SysWrRdy, signal 41, 118
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