MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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I- 8 Index floating-point adder 9 floating-point multiplier 9 instruction decode and rename 10 integer ALU 9 iterative 9 Load/Store Unit 9 G G, (Global) bit in TLB 240, 330 gathering data, in identical mode 92 gathering data, in sequential mode 92 global processes (G bit in TLB) 330 graduation definition of 373 of an instruction 371 Grant parking 108 H hardware emulation, support for 154 hardware interrupts 105 hazards, CP0 285 Hit Writeback Invalidate CACHE instruction 199 hold times, AC electrical 216 I I/O signals, DC characteristics 214 I/O, support for 152 IC, (instruction cache size) field 256 IE, (interrupt enable) bit 249 IE, bit 265 IM, (interrupt mask) field 247 implementation number, R10000 processor 255 incoming buffer 89, 90 Index Hit Invalidate CACHE instruction 197 Index Invalidate CACHE instruction 192 Index Load Data CACHE instruction 201 Index Load Tag CACHE instruction 194, 195, 197, 198, 199, 201, 202 Index Load Tag instruction 72 Index register 237 Index Store Data CACHE instruction 74, 202 Index Store Tag CACHE instruction 77, 195 Index Writeback Invalidate CACHE instruction 192 indexing, the secondary cache 62 inexact result (FP) 310 initialization 159 input voltage levels, maximum 217 instruction CACHE, see also CACHE instructions 172, 187, 285, 287 CacheOp, see also CACHE instructions 287 completion 20, 371 COP0 see also CP0 357 COP1 357 COP2 357 decoding 371 dependencies 13 DMFC0 285, 290 DMFC1 310 DMTC0 285, 291 ERET 285, 292 execution 371 fetching 371 FPU, processor specific 312 CFC1 313 CTC1 313 CVT.L.fmt 312 for valid FP control registers 313 moves and conditional moves 313 graduation 371 issue 20, 371 superscalar 20 latencies 29 load linked 27 MFC0 285, 293 MFC1 307, 310 MFPC 295 MFPS 295 MTC0 285, 296 MTPC 295 MTPS 295 prefetch 25 processor-specific 26 queue 11, 17 repeat rates 29 serializing 23, 190 store conditional 27 SWC1 307 SYNC 28, 56, 148 TLBP 285, 297 TLBR 285, 298 TLBWI 285, 299 Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
Index I-9 TLBWR 285, 300 unsupported CACHE 190 instruction cache, block size see also cache, primary instruction 46 instruction register, JTAG 205 integer queue 11 branch instructions 11 divide instructions 11 multiply instructions 11 ports 11 shift instructions 11 integer ALU pipeline 6 Integer Overflow exception 347 integer queue 6 interface, external 10 internal coherency conflicts 143 internal processor clock domain 156 Interrupt exception 355 interrupt mask, bit 244 Interrupt register 105 interrupt request, external 105 interrupts 105 hardware 105 nonmaskable 106 software 106 timer 106 invalid operation, FP 310 invalidate request, external 135 invalidation, and CACHE instructions 190 IP, (interrupt pending) bit 252, 273 ISA (Instruction Set Architecture) MIPS I 2 MIPS II 2 MIPS III 2 MIPS IV 2, 303 issue, dynamic 371 issuing, an instruction 371 iterative execution units 375 ITLB (instruction TLB) 330 ITLBM, field 261 J JTAG boundary scan register 206 bypass register 205 Capture-DR state 206 instruction register 205 interface 203 instruction register 205 JTCK signal 204 JTDI signal 204 JTDO signal 204 JTMS signal 204 Tap controller 204 test access port 204 Shift-DR state 205, 206 signals 43 Update-DR state 206 Update-IR state 205 JTCK, signal 43, 204, 213 JTDI, signal 43, 204, 205, 213 JTDO, signal 43, 204, 205 JTLB (joint TLB) 330 JTMS, signal 43, 204, 213 K K0, field 256 Kernel mode 316 address mapping 322 ckseg0 space 326 ckseg1 space 326 ckseg3 space 326 cksseg space 326 kseg0 space 323 kseg1 space 323 kseg3 space 323 ksseg space 323 kuseg space 323 operations 322 xkphys space 324 xkseg space 326 xksseg space 324 xkuseg space 324 kseg0 space 323 Kseg0CA, mode bits 164 kseg1 space 323 kseg3 space 323 ksseg space 323 KSU, field 247, 249, 332 MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Coprocessor 0 273 14.21 ECC Registe
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Coprocessor 0 275 CacheErr Register
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Coprocessor 0 277 CacheErr Register
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Coprocessor 0 279 Errata Primary In
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Coprocessor 0 281 Errata Errata Sec
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Coprocessor 0 283 Primary Data Cach
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Coprocessor 0 285 14.25 CP0 Instruc
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Coprocessor 0 287 14.27 CACHE Instr
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Coprocessor 0 289 Cache CACHE (cont
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Coprocessor 0 291 14.29 DMTC0 Instr
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Coprocessor 0 293 14.31 MFC0 Instru
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Coprocessor 0 295 MTPS 31 Format: M
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Coprocessor 0 297 14.34 TLBP Instru
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Coprocessor 0 299 14.36 TLBWI Instr
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15. Floating-Point Unit This sectio
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Floating-Point Unit 303 15.2 Floati
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Floating-Point Unit 305 Load and St
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Floating-Point Unit 307 63 63 Doubl
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Floating-Point Unit 309 Floating-Po
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Floating-Point Unit 311 Loading the
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Floating-Point Unit 313 Moves and C
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16. Memory Management This section
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Memory Management 317 Addressing Mo
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Memory Management 319 32-bit User M
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Memory Management 321 32-bit Superv
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Memory Management 323 32-bit Kernel
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Memory Management 325 0X BFFFFFFF 0
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Memory Management 327 64-bit Virtua
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Memory Management 329 Using the TLB
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17. CPU Exceptions This chapter des
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Page 367 and 368: CPU Exceptions 337 Soft † Reset E
Page 369 and 370: CPU Exceptions 339 NMI Exception Ca
Page 371 and 372: CPU Exceptions 341 TLB Exceptions T
Page 373 and 374: CPU Exceptions 343 TLB Invalid Exce
Page 375 and 376: CPU Exceptions 345 Cache Error Exce
Page 377 and 378: CPU Exceptions 347 Integer Overflow
Page 379 and 380: CPU Exceptions 349 System Call Exce
Page 381 and 382: CPU Exceptions 351 Reserved Instruc
Page 383 and 384: CPU Exceptions 353 Floating-Point E
Page 385 and 386: CPU Exceptions 355 Interrupt Except
Page 387 and 388: CPU Exceptions 357 17.5 COP0 Instru
Page 389 and 390: 18. Cache Test Mode The R10000 proc
Page 391 and 392: Cache Test Mode 361 18.3 Entering C
Page 393 and 394: Cache Test Mode 363 18.5 SysAD(63:0
Page 395 and 396: Cache Test Mode 365 Auto-Increment
Page 397 and 398: Cache Test Mode 367 Auto-Increment
Page 399 and 400: A. Glossary The following terms are
Page 401 and 402: A.6 Dynamic Scheduling The R10000 p
Page 403 and 404: A.11 Nonblocking Loads and Stores M
Page 405 and 406: A.13 Logical and Physical Registers
Page 407 and 408: Index I-1 Index Numerics 16-word, c
Page 409 and 410: Index I-3 uncached accelerated, des
Page 411 and 412: Index I-5 branch on CP0 instruction
Page 413: Index I-7 F fetch pipeline 6, 17 fe
Page 417 and 418: Index I-11 NMI see also nonmaskable
Page 419 and 420: Index I-13 CP0 (description of) 235
Page 421 and 422: Index I-15 SysAD[20:16] interrupt r
Page 423 and 424: Index I-17 SysWrRdy, signal 41, 118
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