MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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I- 6 Index ERR completion response 130 ERR, signal 90 error correctable 168 handling 167 protocol 185 levels, in the Status register 316 protection 167 schemes used in R10000 173 protection schemes, used in R10000 ECC 173 parity 173 sparse encoding 173 uncorrectable 169 handling an 171 limiting the propagation of 170 units that detect and report uncorrectable errors 171 error correcting code see also ECC 173 Error Exception Program Counter (ErrorEPC) register 284 Event, field 265 EW, bit in CacheErr register 172 ExcCode, field 252, 253 exception levels, in the Status register 316 exception processing, CPU exception types Address Error 340 Breakpoint 350 Bus Error 346 Cache Error 171, 345 Coprocessor Unusable 352 Floating-Point 353 Integer Overflow 347 Interrupt 355 NMI 339 Reserved Instruction 351 Soft Reset 337 System Call 349 TLB 341 TLB Invalid 341, 343 TLB Modified 341, 344 TLB Refill 341, 342 Trap 348 Virtual Coherency 345 Watch 354 exception vector location Reset 332 TLB Refill 332 exception vector selection 333 precise handling 15 priority of 333, 335 TLB refill vector locations 334 Exception Program Counter (EPC) register 254 Exception Return, instruction 285 executing, an instruction 371 execution order 13 execution pipelines 6 execution units, iterative 375 execution, speculative 20, 374 EXL, (exception level) bit 249, 254, 316, 332 external ACK completion response 90, 130 external agent 34, 35, 79 also referred to as cluster coordinator 81 connecting to 81 external allocate request number request protocol 134 external block data response 94, 128 protocol 127 external coherency conflicts 144 external coherency request latency 146 external coherency requests, action taken 142 external completion response 131 protocol 130 external double/single/partial-word data response protocol 129 external duplicate tags, support for 152 external interface 10 memory accesses 32 priority operations 32 external interrupt request 105 protocol 136 external intervention exclusive request 141 external intervention request 133 protocol 133 external intervention shared request 141 external invalidate request 141 protocol 135 external NACK completion response 130 external request 80, 87 protocol 132 external response 80, 87 protocol 127 Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
Index I-7 F fetch pipeline 6, 17 fetching, an instruction 371 FGR (Floating-Point General register) 32-bit operations 304 5-bit select 303 64-bit operations 304 load operations 305 operations 304 Status register FR bit 304 store operations 305 Fill, field 245 flag uncorrectable error 90 Flag, field (FP) 310 floating-point adder 18 adder pipeline 6 divide 18, 302 multiplier 18 pipeline 7 queue 6, 11 instructions written each cycle 11 number of allowable entries 11 ports 11 sequencing 11 registers 303 rounding mode 311 square root 18 Floating-Point exception 353 Floating-Point Status register see also FSR 309 Floating-Point Unit, see also FPU 301 flow control 93 external data response 93 external request 93 processor coherency data response 93 processor eliminate request 93 processor read request 93 processor upgrade request 93 processor write request 93 signals 41 format, TLB entry 329 FPU 301 Active List, control of FSR 309 add unit 301 arithmetic instructions 310 cause bits, FSR 310 changing rounding mode using a CTC1 311 compare 310 condition bits 310 control registers 308 divide unit 301 FGRs (general registers) 303 FSR, (Status register in FPU) 309 graduation, control of FSR 309 instructions, processor specific 312 latency 301 logic diagram 302 move to floating-point 307 multiply unit 301 operations 302 queue controlling units 303 move unit, FPU 302 read ports 302 register file 302 repeat rate 301 rounding modes 311 serial dependency circuit 307 square-root unit 301 FR, field 248 FrameMask register 240, 260 free list 372 freeing the request number, with completion response 130 FSR (Floating-Point Status register) cause bits 310 condition bits 310 division by zero 310 enable bits 310 flag bits 310 inexact result 310 invalid operation 310 load exceptions 311 loading the FSR 311 overflow 310 RM, round to minus infinity 311 RN, round to nearest representable value 311 RP, round to plus infinity 311 RZ, round toward zero 311 underflow 310 unimplemented operation 310 functional unit 9 branch 10 MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Coprocessor 0 273 14.21 ECC Registe
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Coprocessor 0 275 CacheErr Register
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Coprocessor 0 277 CacheErr Register
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Coprocessor 0 279 Errata Primary In
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Coprocessor 0 281 Errata Errata Sec
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Coprocessor 0 283 Primary Data Cach
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Coprocessor 0 285 14.25 CP0 Instruc
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Coprocessor 0 287 14.27 CACHE Instr
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Coprocessor 0 289 Cache CACHE (cont
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Coprocessor 0 291 14.29 DMTC0 Instr
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Coprocessor 0 293 14.31 MFC0 Instru
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Coprocessor 0 295 MTPS 31 Format: M
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Coprocessor 0 297 14.34 TLBP Instru
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Coprocessor 0 299 14.36 TLBWI Instr
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15. Floating-Point Unit This sectio
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Floating-Point Unit 303 15.2 Floati
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Floating-Point Unit 305 Load and St
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Floating-Point Unit 307 63 63 Doubl
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Floating-Point Unit 309 Floating-Po
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Floating-Point Unit 311 Loading the
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Floating-Point Unit 313 Moves and C
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16. Memory Management This section
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Memory Management 317 Addressing Mo
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Memory Management 319 32-bit User M
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Memory Management 321 32-bit Superv
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Memory Management 323 32-bit Kernel
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Memory Management 325 0X BFFFFFFF 0
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Memory Management 327 64-bit Virtua
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Memory Management 329 Using the TLB
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Page 373 and 374: CPU Exceptions 343 TLB Invalid Exce
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Page 377 and 378: CPU Exceptions 347 Integer Overflow
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Page 383 and 384: CPU Exceptions 353 Floating-Point E
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Page 387 and 388: CPU Exceptions 357 17.5 COP0 Instru
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Page 391 and 392: Cache Test Mode 361 18.3 Entering C
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Page 395 and 396: Cache Test Mode 365 Auto-Increment
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Page 399 and 400: A. Glossary The following terms are
Page 401 and 402: A.6 Dynamic Scheduling The R10000 p
Page 403 and 404: A.11 Nonblocking Loads and Stores M
Page 405 and 406: A.13 Logical and Physical Registers
Page 407 and 408: Index I-1 Index Numerics 16-word, c
Page 409 and 410: Index I-3 uncached accelerated, des
Page 411: Index I-5 branch on CP0 instruction
Page 415 and 416: Index I-9 TLBWR 285, 300 unsupporte
Page 417 and 418: Index I-11 NMI see also nonmaskable
Page 419 and 420: Index I-13 CP0 (description of) 235
Page 421 and 422: Index I-15 SysAD[20:16] interrupt r
Page 423 and 424: Index I-17 SysWrRdy, signal 41, 118
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