MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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I- 4 Index unsupported instructions 190 using the physical address 188 using the virtual address 188 cache miss stalls 25 Cache Operation, see also CACHE instructions 285 cache test mode entry 361 exit 362 cacheable coherent exclusive on write, cache algorithm 53, 54 cacheable coherent exclusive, cache algorithm 53, 54 cacheable noncoherent, cache algorithm 53, 54 cached request buffer 89 CacheErr register 171, 172, 174, 175, 274 CacheOp, see also CACHE instructions 187, 287 capacitors, decoupling 218 cause bits, FPU 310 Cause register 105, 106, 244, 252, 254 Cause, field (FP) 310 CE, bit 190, 249, 250, 252 CH, bit 190, 250, 285 chip revisions, R10000 255 ckseg0 space 326 ckseg1 space 326 ckseg3 space 326 cksseg space 326 CLGA (ceramic land grid array) 220 electrical characteristics 221 layout 220 mechanical characteristics 220 package 220 pinout 224 thermal characteristics 222 clock domain in secondary cache 157 internal processor clock domain 155 secondary cache clock domain 155 System interface clock domain 155 signal PClk 156 SCClk 157 SysClk 155 SysClkRET 156 signals, overview of 41 clock divisor, system interface 80, 360 cluster bus 36, 82 operation 148 cluster coordinator 81, 82 cluster request buffer 89 coherency conflicts 143 coherency protocol, directory-based 153 coherency request, external 138, 140 coherency schemes 36 coherency, System interface external intervention exclusive request 141 external intervention shared request 141 external invalidate request 141 CohPrcReqTar, mode bit 102, 149, 152, 164 cold reset 159 sequence 162 Cold Reset exception 332 Compare register 106, 244 completing, an instruction 371 completion, definition of 373 condition bit dependencies 14 Condition, field (FP) 310 conditional move instruction (FP) 313 Config register 256 conflicts coherency 143 internal 143 TLB, avoiding 330 Context register 241, 259 context switch 330 control registers, FPU 308 controller, TAP 204 coordinator, cluster 81 COP1 instructions 357 COP2 instructions 357 Coprocessor 0, see also CP0 235 Coprocessor 1 see also CP1, COP1 251 Coprocessor 2 see also CP2, COP2 251 Coprocessor 3 see also CP3, COP3 251 Coprocessor Unusable exception 352 correctable error 168 Count register 106, 244 CP0 (coprocessor 0) 235 Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
Index I-5 branch on CP0 instructions 285 hazards 285 instructions 285, 357 load hazards 285 move instructions 286 registers, list of 236 csseg space 321 CT, bit 256 CTM, mode bit 166, 361, 362 CU, (coprocessor usability) field 246, 248, 251 CVT.L.fmt instruction 312 D D, (dirty) bit 239 data cache see also cache, primary data 48 data dependencies 20 data path, secondary cache 10 data quality indication 92 DBRC, field 261 DC characteristics of I/O signals 214 DC electrical specifications 210 input and output 214 input level sensing 212 maximum operating conditions 211 mode definitions 212 power supply levels 210 unused inputs 213 Vref, voltage reference 212 DC power supply levels 210 DC voltage, reference 212 DC, (data cache size) field 256 DCOk, signal 38, 160, 211, 212, 217 DE, bit 172, 250 debugging, and Watch registers 258 decoding, an instruction 371 decoupling capacitance 218 delay times, AC electrical 216 dependencies condition bit 14 exception 15 instruction 13 memory 14 pipeline 13 register 14, 375 DevNum, mode bits 164 Diagnostic register 261 directory-based coherency protocol 153 divide unit, FPU 301 division by zero, FP 310 divisor, clock, system interface 80, 360 DMFC0, instruction 286, 290 DMTC0, instruction 286, 291 DN, (device number) field 256 Done, bit 11 done, see also completion 373 Doubleword Move From CP0, instruction 285 Doubleword Move To CP0, instruction 285 DP, (primary data cache parity) field 273 DS, (diagnostic status) field 247, 248, 249 duplicate tags, external 34 dynamic issue 13, 371 dynamic scheduling 371 MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997 E EC, field 256 ECC (error correcting code) matrix for secondary cache data array 177 matrix for secondary cache tag array 179 matrix for System interface 183 register 273 secondary cache 10 ECC register 69, 74 ECC, field 273 efficiency, program, suggestions for increasing 21 electrical specifications AC 215 DC 210 Enable, field (FP) 310 enable/output delay 216 EntryHi register 245, 329 ASID field in 330 EntryLo registers, and FrameMask register 260 EntryLo0 register 239, 329 EntryLo1 register 239, 329 EPC register 254 ERET, instruction 292 ERL, (error level) bit 171, 249, 316
Page 1 and 2:
MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Coprocessor 0 273 14.21 ECC Registe
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Coprocessor 0 275 CacheErr Register
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Coprocessor 0 277 CacheErr Register
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Coprocessor 0 279 Errata Primary In
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Coprocessor 0 281 Errata Errata Sec
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Coprocessor 0 283 Primary Data Cach
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Coprocessor 0 285 14.25 CP0 Instruc
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Coprocessor 0 287 14.27 CACHE Instr
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Coprocessor 0 289 Cache CACHE (cont
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Coprocessor 0 291 14.29 DMTC0 Instr
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Coprocessor 0 293 14.31 MFC0 Instru
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Coprocessor 0 295 MTPS 31 Format: M
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Coprocessor 0 297 14.34 TLBP Instru
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Coprocessor 0 299 14.36 TLBWI Instr
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15. Floating-Point Unit This sectio
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Floating-Point Unit 303 15.2 Floati
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Floating-Point Unit 305 Load and St
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Floating-Point Unit 307 63 63 Doubl
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Floating-Point Unit 309 Floating-Po
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Floating-Point Unit 311 Loading the
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Floating-Point Unit 313 Moves and C
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16. Memory Management This section
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Memory Management 317 Addressing Mo
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Memory Management 319 32-bit User M
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Memory Management 321 32-bit Superv
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Memory Management 323 32-bit Kernel
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Memory Management 325 0X BFFFFFFF 0
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Memory Management 327 64-bit Virtua
Page 359 and 360: Memory Management 329 Using the TLB
Page 361 and 362: 17. CPU Exceptions This chapter des
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Page 367 and 368: CPU Exceptions 337 Soft † Reset E
Page 369 and 370: CPU Exceptions 339 NMI Exception Ca
Page 371 and 372: CPU Exceptions 341 TLB Exceptions T
Page 373 and 374: CPU Exceptions 343 TLB Invalid Exce
Page 375 and 376: CPU Exceptions 345 Cache Error Exce
Page 377 and 378: CPU Exceptions 347 Integer Overflow
Page 379 and 380: CPU Exceptions 349 System Call Exce
Page 381 and 382: CPU Exceptions 351 Reserved Instruc
Page 383 and 384: CPU Exceptions 353 Floating-Point E
Page 385 and 386: CPU Exceptions 355 Interrupt Except
Page 387 and 388: CPU Exceptions 357 17.5 COP0 Instru
Page 389 and 390: 18. Cache Test Mode The R10000 proc
Page 391 and 392: Cache Test Mode 361 18.3 Entering C
Page 393 and 394: Cache Test Mode 363 18.5 SysAD(63:0
Page 395 and 396: Cache Test Mode 365 Auto-Increment
Page 397 and 398: Cache Test Mode 367 Auto-Increment
Page 399 and 400: A. Glossary The following terms are
Page 401 and 402: A.6 Dynamic Scheduling The R10000 p
Page 403 and 404: A.11 Nonblocking Loads and Stores M
Page 405 and 406: A.13 Logical and Physical Registers
Page 407 and 408: Index I-1 Index Numerics 16-word, c
Page 409: Index I-3 uncached accelerated, des
Page 413 and 414: Index I-7 F fetch pipeline 6, 17 fe
Page 415 and 416: Index I-9 TLBWR 285, 300 unsupporte
Page 417 and 418: Index I-11 NMI see also nonmaskable
Page 419 and 420: Index I-13 CP0 (description of) 235
Page 421 and 422: Index I-15 SysAD[20:16] interrupt r
Page 423 and 424: Index I-17 SysWrRdy, signal 41, 118
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