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MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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Index I-3<br />

uncached accelerated, description of 55<br />

uncached, description of 54<br />

where specified 53<br />

associativity 45<br />

block ownership 58<br />

misses 25<br />

nonblocking 23, 25<br />

ordering constraints 15<br />

pages 328<br />

primary 4<br />

primary data 9<br />

block size 48<br />

changing states 49<br />

description of 48<br />

diagram, state 50<br />

error handling 175<br />

index and tag 49<br />

interleaving 32<br />

refill 31<br />

state diagram 50<br />

states 49<br />

subset of secondary cache 49<br />

write back protocol 48<br />

primary instruction 9<br />

block size 46<br />

description of 46<br />

diagram, state 47<br />

error handling 174<br />

error protection 174<br />

index and tag 46<br />

refill 31<br />

state diagram 47<br />

states 46<br />

rules, ownership of a cache block 58<br />

secondary 4<br />

associativity 10, 51<br />

block size 51<br />

block state 67<br />

blocks 10<br />

changing states 52<br />

clock domain 157<br />

data array 60<br />

data array width 62<br />

description of 51<br />

diagram, state 52<br />

ECC 10<br />

error handling 176<br />

index and tag 51<br />

indexing 62<br />

indexing the data array 62<br />

indexing the tag array 63<br />

interface frequencies 61<br />

sizes 10<br />

specifying block size 60<br />

specifying cache size 60<br />

state diagram 52<br />

states 51<br />

tag 66<br />

tag and data array ECC 60<br />

tag array 60<br />

way prediction 64<br />

way prediction table 63<br />

write back protocol 51<br />

strong ordering<br />

example of 16<br />

structure, two-level 45<br />

Cache Barrier CACHE instruction 198<br />

Cache Error exception 171, 345<br />

precision 171<br />

prioritization 171<br />

Cache Error handler 171<br />

CACHE instruction<br />

support for I/O 152<br />

CACHE instructions 172, 187, 188, 287<br />

and a hit in the cache 189<br />

and Address Error exception 189<br />

and CE bit 190<br />

and CH bit 190<br />

and CP0 188<br />

and invalidation 190<br />

and TLB Invalid exception 189<br />

and TLB Refill exception 189<br />

and Watch exception 189<br />

and write back 189<br />

Cache Barrier 198<br />

effect on the uncached buffer 92<br />

Hit Writeback Invalidate 199<br />

Index Hit Invalidate 197<br />

Index Invalidate 192<br />

Index Load Data 201<br />

Index Load Tag 194, 195, 197, 198, 199, 201, 202<br />

Index Store Data 202<br />

Index Store Tag 195<br />

Index Writeback Invalidate 192<br />

op field encoding 191<br />

serial operations 190<br />

<strong>MIPS</strong> <strong>R10000</strong> <strong>Microprocessor</strong> <strong>User's</strong> <strong>Manual</strong> Version 2.0 of January 29, 1997

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