MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

I- 2 Index
ALU1 9, 11
ALU2 9, 11
ANDES, Architecture with Non-sequential Dynamic
Execution Scheduling 4, 375
arbitration protocol, System interface 108
arbitration rules, System interface 109
arbitration signals 41
arbitration, cluster bus 82
Architecture with Non-sequential Dynamic Execution
Scheduling, see also ANDES 375
arithmetic instructions, FPU 310
arithmetic logic unit, see also ALU 18
array 62
array, page table entry (PTE) 241
ASID (Address Space Identifier)
context switch 330
relationship to Global (G) bit in TLB entry 330
ASID (Address Space Indentifier)
stored in EntryHi register 330
ASID, field 245
asynchronous inputs, AC electrical specification 216
auto-increment read, cache test mode 367
auto-increment write, cache test mode 365
B
Bad Virtual Address register (BadVAddr) 244
BadVAddr register 241, 259, 340
BadVPN2, field 241, 259
BD, (branch delay) bit 252, 254
BE, (memory endianness) bit 256
BEV, (boot exception vector) bit 250
BEV, bit 171, 332
block
instruction cache 9
primary data cache 9
secondary cache 10
size
primary data cache 48
primary instruction cache 46
secondary cache 51
block data transfers 94
external block data responses 94
processor block write requests 94
processor coherency data responses 94
boundary scan register, JTAG 206
BPIdx, field 262
BPMode, field 261
BPOp, field 262
BPState, field 262
branch
determining next address 17
instruction, limits on execution 17
prediction 14, 31, 374
prediction rates, improving 21
speculative 374
unit 10, 17
Branch on Coprocessor 0 instructions 285
BRCH, field 261
BRCV, field 261
BRCW, field 261
Breakpoint exception 350
BSIdx, field 261
buffer
cached request 89
cluster request 89
incoming 89, 90
outgoing 89, 91
uncached 89, 92
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
bus
SysAD 102
SysCmd 95
SysResp 105
SysState 104
Bus Error exception 346
busy-bit table 372
bypass register, JTAG 205
C
C, (coherency attribute) bit 239
cache 4
algorithms 53
and processor requests 57
cacheable coherent exclusive on write, description
of 54
cacheable coherent exclusive, description of 54
cacheable noncoherent, description of 54
fields, encoding of 53
for kseg0 address space 53
for mapped address space 53
for xkphys address space 53