MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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364 Chapter 18. 18.6 Cache Test Mode Protocol Normal Write Protocol Cycle SysClk Master SysReset* SysGnt* SysAD(63:0) SysVal* This section describes the cache test mode protocol in detail, including: • normal write protocol • auto-increment protocol • normal read protocol • auto-increment read protocol A cache test mode normal write operation writes a selected RAM array. The write address, way, array, and data are specified in the write command. The external agent issues a normal write command by: • driving the address on SysAD(57:46) • driving the way on SysAD(45) • negating the auto-increment select on SysAD(44) • asserting the Write/Read select on SysAD(43) • driving the array select on SysAD(42:40) • driving the write data on SysAD(39:0) • asserting SysVal* for one SysClk cycle Normal writes have a repeat rate of 8 PClk cycles. Figure 18-3 depicts two cache test mode normal writes. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 EA EA EA EA EA EA EA EA EA EA EA EA EA EA EA EA EA NrmWr NrmWr Figure 18-3 Cache Test Mode Normal Write Protocol Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
Cache Test Mode 365 Auto-Increment Write Protocol Cycle SysClk Master SysReset* SysGnt* SysAD(63:0) SysVal* A cache test mode auto-increment write operation writes a selected RAM array. The write address is obtained by incrementing the previous write address, and the write way is obtained from the previous write way. If an overflow occurs when incrementing the previous write address, the address wraps to 0, and the way is toggled. The write data is identical to the previous write data. For proper results, an auto-increment write must always be proceeded by a normal or auto-increment write. The external agent issues an auto-increment write command by: • asserting the auto-increment select on SysAD(44) • asserting the Write/Read select on SysAD(43) • driving the array select on SysAD(42:40) • asserting SysVal* for one SysClk cycle Auto-increment writes have a repeat rate of one PClk cycle. Figure 18-4 depicts three cache test mode auto-increment writes. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 EA EA EA EA EA EA EA EA EA EA EA EA EA EA EA EA EA IncWr IncWr IncWr Figure 18-4 Cache Test Mode Auto-Increment Write Protocol MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Coprocessor 0 273 14.21 ECC Registe
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Coprocessor 0 275 CacheErr Register
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Coprocessor 0 277 CacheErr Register
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Coprocessor 0 279 Errata Primary In
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Coprocessor 0 281 Errata Errata Sec
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Coprocessor 0 283 Primary Data Cach
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Coprocessor 0 285 14.25 CP0 Instruc
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Coprocessor 0 287 14.27 CACHE Instr
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Coprocessor 0 289 Cache CACHE (cont
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Coprocessor 0 291 14.29 DMTC0 Instr
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Coprocessor 0 293 14.31 MFC0 Instru
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Coprocessor 0 295 MTPS 31 Format: M
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Coprocessor 0 297 14.34 TLBP Instru
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Coprocessor 0 299 14.36 TLBWI Instr
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15. Floating-Point Unit This sectio
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Floating-Point Unit 303 15.2 Floati
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Floating-Point Unit 305 Load and St
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Floating-Point Unit 307 63 63 Doubl
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Floating-Point Unit 309 Floating-Po
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Floating-Point Unit 311 Loading the
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Page 373 and 374: CPU Exceptions 343 TLB Invalid Exce
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Page 389 and 390: 18. Cache Test Mode The R10000 proc
Page 391 and 392: Cache Test Mode 361 18.3 Entering C
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Page 405 and 406: A.13 Logical and Physical Registers
Page 407 and 408: Index I-1 Index Numerics 16-word, c
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Page 411 and 412: Index I-5 branch on CP0 instruction
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