MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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362 Chapter 18. 18.4 Exit Sequence Cycle SysClk Master SysReset* SysGnt* SysAD(63:0) SysVal* SysRespVal* To leave cache test mode, the external agent does the following: • loads the mode bits into the processor by driving the mode bits (with the CTM mode bit negated) on SysAD(63:0) • waits at least two SysClk cycles • asserts SysGnt* for at least one SysClk cycle After at least one SysClk cycle, the external agent may negate SysReset* to end the reset sequence. Figure 18-2 shows the cache test mode exit sequence. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 EA EA EA EA EA EA EA EA EA EA EA EA EA EA EA EA EA Modes Negate CTM mode bit Figure 18-2 Cache Test Mode Exit Sequence Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
Cache Test Mode 363 18.5 SysAD(63:0) Encoding SysAD Bit 0 Data Cache Data Array Encoding of the SysAD(63:0) bus during cache test mode is shown in Table 18-1. “Unused” fields are read as “undefined,” and must be written as zeroes. Table 18-1 Cache Test Mode SysAD(63:0) Encoding Data Cache Tag Array Tag parity Instruction Cache Data Array Instruction Cache Tag Array 1 SCWay Unused 2 State parity 3 LRU LRU 4 5 Data Unused Data Unused Tag parity MRU State parity 6 State State 7 Unused 31:8 35:32 Data parity 36 38:37 Unused Tag Tag StateMod 39 Unused 42:40 Data parity Unused Unused MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997 Secondary Cache Way Predication Array Unused 0 1 2 3 4 Array select 43 Write/Read select 44 Auto-increment select 45 Way 57:46 Address 63:58 Unused
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Coprocessor 0 273 14.21 ECC Registe
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Coprocessor 0 275 CacheErr Register
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Coprocessor 0 277 CacheErr Register
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Coprocessor 0 279 Errata Primary In
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Coprocessor 0 281 Errata Errata Sec
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Coprocessor 0 283 Primary Data Cach
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Coprocessor 0 285 14.25 CP0 Instruc
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Coprocessor 0 287 14.27 CACHE Instr
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Coprocessor 0 289 Cache CACHE (cont
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Coprocessor 0 291 14.29 DMTC0 Instr
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Coprocessor 0 293 14.31 MFC0 Instru
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Coprocessor 0 295 MTPS 31 Format: M
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Coprocessor 0 297 14.34 TLBP Instru
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Coprocessor 0 299 14.36 TLBWI Instr
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15. Floating-Point Unit This sectio
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Floating-Point Unit 303 15.2 Floati
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Floating-Point Unit 305 Load and St
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Floating-Point Unit 307 63 63 Doubl
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Floating-Point Unit 309 Floating-Po
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Page 347 and 348: Memory Management 317 Addressing Mo
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Page 363 and 364: CPU Exceptions 333 17.3 TLB Refill
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Page 377 and 378: CPU Exceptions 347 Integer Overflow
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Page 389 and 390: 18. Cache Test Mode The R10000 proc
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Page 403 and 404: A.11 Nonblocking Loads and Stores M
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Page 407 and 408: Index I-1 Index Numerics 16-word, c
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Page 417 and 418: Index I-11 NMI see also nonmaskable
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Page 423 and 424: Index I-17 SysWrRdy, signal 41, 118
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