MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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334 Chapter 17. Table 17-2 lists the TLB refill vector locations, based on the address that caused the TLB miss and its corresponding mode bit. Table 17-2 TLB Refill Vectors Space Address Range Regions Kernel Supervisor Kernel Supervisor User User 0xFFFF FFFF E000 0000 to 0xFFFF FFFF FFFF FFFF kseg3 0xFFFF FFFF C000 0000 to 0xFFFF FFFF DFFF FFFF 0xC000 0000 0000 0000 to 0xC000 0FFE FFFF FFFF 0x4000 0000 0000 0000 to 0x4000 0FFF FFFF FFFF 0x0000 0000 8000 0000 to 0x0000 0FFF FFFF FFFF 0x0000 0000 0000 0000 to 0x0000 0000 7FFF FFFF sseg, ksseg Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual Exception Vector Refill (KX=0) or XRefill (KX=1) Refill (KX=0) or XRefill (KX=1) xkseg XRefill(KX=1) xsseg, xksseg XRefill (SX=1) xsuseg, xuseg, xkuseg useg, xuseg, suseg, xsuseg, kuseg, xkuseg XRefill (UX=1) Refill (UX=0) or XRefill (UX=1)
CPU Exceptions 335 Priority of Exceptions The remainder of this chapter describes exceptions in the order of their priority shown in Table 17-3 (with certain of the exceptions, such as the TLB exceptions and Instruction/Data exceptions, grouped together for convenience). While more than one exception can occur for a single instruction, only the exception with the highest priority is reported. Some exceptions are not caused by the instruction executed at the time, and some exceptions may be deferred. See the individual description of each exception in this chapter for more detail. Table 17-3 Exception Priority Order Cold Reset (highest priority) Soft Reset Nonmaskable Interrupt (NMI) ‡ Cache error –– Instruction cache * Cache error –– Data cache * Cache error –– Secondary cache * Cache error –– System interface * Address error –– Instruction fetch TLB refill –– Instruction fetch TLB invalid –– Instruction fetch Bus error –– Instruction fetch Integer overflow, Trap, System Call, Breakpoint, Reserved Instruction, Coprocessor Unusable, or Floating-Point Exception Address error –– Data access TLB refill –– Data access TLB invalid –– Data access TLB modified –– Data write Watch * Bus error –– Data access Interrupt (lowest priority) * ‡ These exceptions are interrupt types, and may be imprecise. Priority may not be followed when considering a specific instruction. Generally speaking, the exceptions described in the following sections are handled (“processed”) by hardware; these exceptions are then serviced by software. MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Coprocessor 0 273 14.21 ECC Registe
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Coprocessor 0 275 CacheErr Register
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Coprocessor 0 277 CacheErr Register
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Coprocessor 0 279 Errata Primary In
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Coprocessor 0 281 Errata Errata Sec
Page 313 and 314: Coprocessor 0 283 Primary Data Cach
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Page 317 and 318: Coprocessor 0 287 14.27 CACHE Instr
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Page 323 and 324: Coprocessor 0 293 14.31 MFC0 Instru
Page 325 and 326: Coprocessor 0 295 MTPS 31 Format: M
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Page 331 and 332: 15. Floating-Point Unit This sectio
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Page 357 and 358: Memory Management 327 64-bit Virtua
Page 359 and 360: Memory Management 329 Using the TLB
Page 361 and 362: 17. CPU Exceptions This chapter des
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Page 373 and 374: CPU Exceptions 343 TLB Invalid Exce
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Page 377 and 378: CPU Exceptions 347 Integer Overflow
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Page 389 and 390: 18. Cache Test Mode The R10000 proc
Page 391 and 392: Cache Test Mode 361 18.3 Entering C
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Page 395 and 396: Cache Test Mode 365 Auto-Increment
Page 397 and 398: Cache Test Mode 367 Auto-Increment
Page 399 and 400: A. Glossary The following terms are
Page 401 and 402: A.6 Dynamic Scheduling The R10000 p
Page 403 and 404: A.11 Nonblocking Loads and Stores M
Page 405 and 406: A.13 Logical and Physical Registers
Page 407 and 408: Index I-1 Index Numerics 16-word, c
Page 409 and 410: Index I-3 uncached accelerated, des
Page 411 and 412: Index I-5 branch on CP0 instruction
Page 413 and 414: Index I-7 F fetch pipeline 6, 17 fe
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Index I-9 TLBWR 285, 300 unsupporte
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Index I-11 NMI see also nonmaskable
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Index I-13 CP0 (description of) 235
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Index I-15 SysAD[20:16] interrupt r
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Index I-17 SysWrRdy, signal 41, 118
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