MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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326 Chapter 16. 64-bit Kernel Mode, Kernel Space (xkseg) In Kernel mode, when KX = 1 in the Status register and bits 63:62 of the 64-bit virtual address are 112 , the address space selected is one of the following: • kernel virtual space, xkseg, the current kernel virtual space; the virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address • one of the four 32-bit kernel mode compatibility spaces (described below). 64-bit Kernel Mode, Compatibility Spaces (ckseg1:0, cksseg, ckseg3) In Kernel mode, when KX = 1 in the Status register, bits 63:62 of the 64-bit virtual address are 112 , and bits 61:31 of the virtual address equal –1, the lower two bytes of address, as shown in Figure 16-3, select one of the following 512-Mbyte compatibility spaces. • ckseg0. This 64-bit virtual address space is an unmapped region, compatible with the 32-bit address model kseg0. The K0 field of the Config register controls cacheability and coherency. • ckseg1. This 64-bit virtual address space is an unmapped and uncached region, compatible with the 32-bit address model kseg1. • cksseg. This 64-bit virtual address space is the current supervisor virtual space, compatible with the 32-bit address model ksseg. • ckseg3. This 64-bit virtual address space is kernel virtual space, compatible with the 32-bit address model kseg3. Address Space Access Privilege Differences Between the R4400 and R1000 In the R4400, the 64-bit Supervisor mode can access the entire xsuseg space, and the 64-bit Kernel mode can access the entire xksseg and xkuseg spaces. Access privileges in the R10000 are also dependent on the UX and SX bits: • Access to the 64-bit user space in 64-bit Supervisor or Kernel mode (xsuseg or xkuseg) is controlled by the UX bit. If UX=0, the 64-bit Supervisor and Kernel modes can only access the 32-bit user space (suseg or kuseg). • Access to the 64-bit supervisor space in Kernel mode (xksseg) is controlled by the SX bit. If SX=0, the 64-bit Kernel mode can only access the 32-bit supervisor space (ksseg). An Address Error exception is taken on an illegal access. The R10000 processor implements the same access privileges for 32-bit processor modes as in the R4400. The Table 16-2 summarizes the access privileges for all processor modes in the R10000 processor. Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
Memory Management 327 64-bit Virtual Address FFFFFFFF E0000000 TO FFFFFFFF FFFFFFFF FFFFFFFF C0000000 TO FFFFFFFF DFFFFFFF FFFFFFFF A0000000 TO FFFFFFFF BFFFFFFF FFFFFFFF 80000000 TO FFFFFFFF 9FFFFFFF C0000FFF 00000000 TO FFFFFFFF 7FFFFFFF C0000000 00000000 TO C0000FFE FFFFFFFF 80000000 00000000 TO BFFFFFFF FFFFFFFF 40001000 00000000 TO 7FFFFFFF FFFFFFFF 40000000 00000000 TO 40000FFF FFFFFFFF 00001000 00000000 TO 3FFFFFFF FFFFFFFF 00000000 80000000 TO 00000FFF FFFFFFFF 00000000 00000000 TO 00000000 7FFFFFFF Table 16-2 Access Privileges for User, Supervisor and Kernel Mode Operations User ‡ AddrErr 32-bit Mode 64-bit Mode Supervisor Kernel User Supervisor Kernel & ERL=0 AddrErr ‡ For data references, the upper 32 bits of the virtual addresses are cleared before checking access privilege and TLB translation. MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997 OK AddrErr AddrErr OK OK AddrErr AddrErr OK AddrErr OK Kernel & ERL=1 OK OK AddrErr AddrErr OK OK OK OK AddrErr AddrErr AddrErr if SX=0 AddrErr if SX=0 AddrErr AddrErr AddrErr AddrErr if UX=0 AddrErr if UX=0 AddrErr OK OK OK OK OK OK
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Coprocessor 0 273 14.21 ECC Registe
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Page 389 and 390: 18. Cache Test Mode The R10000 proc
Page 391 and 392: Cache Test Mode 361 18.3 Entering C
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Page 399 and 400: A. Glossary The following terms are
Page 401 and 402: A.6 Dynamic Scheduling The R10000 p
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Index I-1 Index Numerics 16-word, c
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Index I-3 uncached accelerated, des
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Index I-5 branch on CP0 instruction
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Index I-7 F fetch pipeline 6, 17 fe
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Index I-9 TLBWR 285, 300 unsupporte
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Index I-11 NMI see also nonmaskable
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Index I-13 CP0 (description of) 235
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Index I-15 SysAD[20:16] interrupt r
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Index I-17 SysWrRdy, signal 41, 118
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