MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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324 Chapter 16. 64-bit Kernel Mode, User Space (xkuseg) In Kernel mode, when KX = 1 in the Status register and bits 63:62 of the 64-bit virtual address are 002 , selection of the xkuseg virtual address space is dependent upon the UX and ERL bits. • if UX = 1 and ERL = 0, the entire space from 0x0000 0000 0000 0000 through 0000 0FFF FFFF FFFF (16 Tbytes) is selected. • If UX = 0 or ERL = 1, the address space 0x0000 0000 0000 0000 through 0000 0000 7FFF FFFF (2 Gbytes) is selected. Addressing the space ranging from 0000 0000 8000 0000 through 0000 0FFF FFFF FFFF will cause an address error. Moreover, if ERL=1, the selected 2-Gbyte address space becomes unmapped and uncached. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. 64-bit Kernel Mode, Current Supervisor Space (xksseg) In Kernel mode, when KX = 1 in the Status register and bits 63:62 of the 64-bit virtual address are 012 , selection of the xksseg virtual address space is dependent upon the SX bit. • if SX = 1, the entire space from 0x4000 0000 0000 0000 through 4000 0FFF FFFF FFFF (16 Tbytes) is selected. • If SX = 0, access to any address in the space ranging from 0x4000 0000 0000 0000 through 4000 0FFF FFFF FFFF causes an address error. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. 64-bit Kernel Mode, Physical Spaces (xkphys) In Kernel mode, when KX = 1 in the Status register and bits 63:62 of the 64-bit virtual address are 10 2 , the xkphys virtual address space is selected; it is a set of eight kernel physical spaces. Each kernel physical space contains either one or four 2 40 -byte physical pages. References to this space are not mapped; the physical address selected is taken directly from bits 39:0 of the virtual address. Bits 61:59 of the virtual address specify the cache algorithm, described in Chapter 4, the section titled “Cache Algorithms.” If the cache algorithm is either uncached or uncached accelerated (values of 2 or 7) the space contains four physical pages; access to addresses whose bits 56:40 are not equal to 0 cause an Address Error exception. Address bits 58:57 carry the uncached attribute (described in Chapter 6, the section titled “Support for Uncached Attribute”), and are not checked for address errors. If the cache algorithm is neither uncached nor uncached accelerated, the space contains a single physical page, as on the R4400 processor. In this case, access to addresses whose bits 58:40 are not equal to a zero cause an Address Error exception, as shown in Figure 16-4. Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
Memory Management 325 0X BFFFFFFF 0X BE000100 FFFFFFFF 00000000 Address Error 0X9FFFFFFF 0X98000100 FFFFFFFF 00000000 Address Error 0X BE0000FF 0X BE000000 FFFFFFFF 00000000 Uncached Accelerated 0X980000FF 0X98000000 FFFFFFFF 00000000 Cacheable Noncoherent 0X BDFFFFFF 0X BC000100 FFFFFFFF 00000000 Address Error 0X97FFFFFF 0X96000100 FFFFFFFF 00000000 Address Error 0X BC0000FF 0X BC000000 FFFFFFFF 00000000 Uncached Accelerated 0X960000FF 0X96000000 FFFFFFFF 00000000 Uncached 0X BBFFFFFF 0X BA000100 FFFFFFFF 00000000 Address Error 0X95FFFFFF 0X94000100 FFFFFFFF 00000000 Address Error 0X BA0000FF 0X BA000000 FFFFFFFF 00000000 Uncached Accelerated 0X940000FF 0X94000000 FFFFFFFF 00000000 Uncached 0X B9FFFFFF 0X B8000100 FFFFFFFF 00000000 Address Error 0X93FFFFFF 0X92000100 FFFFFFFF 00000000 Address Error 0X B80000FF 0X B8000000 FFFFFFFF 00000000 Uncached Accelerated 0X920000FF 0X92000000 FFFFFFFF 00000000 Uncached 0X B7FFFFFF 0X B0000100 FFFFFFFF 00000000 Address Error 0X91FFFFFF 0X90000100 FFFFFFFF 00000000 Address Error 0X B00000FF FFFFFFFF Reserved ‡ 0X B0000000 00000000 0X900000FF 0X90000000 FFFFFFFF 00000000 Uncached 0X AFFFFFFF 0X A8000100 FFFFFFFF 00000000 Address Error 0X8FFFFFFF 0X88000100 FFFFFFFF 00000000 Address Error 0X A80000FF FFFFFFFF Cacheable Exclusive Write 0X880000FF FFFFFFFF Reserved * 0X A8000000 00000000 0X88000000 00000000 0X A7FFFFFF 0X A0000100 FFFFFFFF 00000000 Address Error 0X87FFFFFF 0X80000100 FFFFFFFF 00000000 Address Error 0X A00000FF FFFFFFFF Cacheable Exclusive 0X800000FF FFFFFFFF Reserved * 0X A0000000 00000000 0X80000000 00000000 ‡ Accessing a reserved space results in undefined behavior. Figure 16-4 xkphys Virtual Address Space MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Page 331 and 332: 15. Floating-Point Unit This sectio
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Page 389 and 390: 18. Cache Test Mode The R10000 proc
Page 391 and 392: Cache Test Mode 361 18.3 Entering C
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Page 395 and 396: Cache Test Mode 365 Auto-Increment
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Page 399 and 400: A. Glossary The following terms are
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A.13 Logical and Physical Registers
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Index I-1 Index Numerics 16-word, c
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Index I-3 uncached accelerated, des
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Index I-5 branch on CP0 instruction
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Index I-7 F fetch pipeline 6, 17 fe
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Index I-9 TLBWR 285, 300 unsupporte
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Index I-11 NMI see also nonmaskable
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Index I-13 CP0 (description of) 235
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Index I-15 SysAD[20:16] interrupt r
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Index I-17 SysWrRdy, signal 41, 118
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