MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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322 Chapter 16. Kernel Mode Operations 32-bit (KSU = 00 or EXL = 1 or ERL = 1) and KX = 0 0x FFFF FFFF 0.5 Gbytes Mapped kseg3 0x E000 0000 0x C000 0000 0x BFFF FFFF 0x A000 0000 0x 9FFF FFFF 0x 8000 0000 0x 7FFF FFFF 0x 0000 0000 0.5 Gbytes Mapped 0.5 Gbytes Unmapped Uncached 0.5 Gbytes Unmapped Cached 2 Gbytes Mapped The processor operates in Kernel mode when the Status register contains the Kernel-mode bit-values shown in Table 16-1. Kernel mode virtual address space is divided into regions differentiated by the high-order bits of the virtual address, as shown in Figure 16-3. ksseg kseg1 kseg0 kuseg Figure 16-3 Kernel Mode Address Space 64-bit (KSU = 00 or EXL = 1 or ERL = 1) and KX = 1 0x FFFF FFFF FFFF FFFF 0x FFFF FFFF E000 0000 0x FFFF FFFF DFFF FFFF 0x FFFF FFFF C000 0000 0x FFFF FFFF BFFF FFFF 0x FFFF FFFF A000 0000 0x FFFF FFFF 9FFF FFFF 0x FFFF FFFF 8000 0000 0x FFFF FFFF 7FFF FFFF 0x C000 0FFF 0000 0000 0x C000 0FFE FFFF FFFF 0x C000 0000 0000 0000 0x BFFF FFFF FFFF FFFF 0x 8000 0000 0000 0000 0x 7FFF FFFF FFFF FFFF 0x 4000 1000 0000 0000 0x 4000 0FFF FFFF FFFF 0x 4000 0000 0000 0000 0x 3FFF FFFF FFFF FFFF 0x 0000 1000 0000 0000 0x 0000 0FFF FFFF FFFF 0x 0000 0000 8000 0000 0x 0000 0000 7FFF FFFF 0x 0000 0000 0000 0000 0.5 Gbytes Mapped 0.5 Gbytes Mapped 0.5 Gbytes Unmapped Uncached 0.5 Gbytes Unmapped Cached Address Error Mapped Unmapped Address Error 16 Tbytes Mapped Address Error 16 Tbytes Mapped (See Note below) NOTE: If ERL = 1, the selected 2 Gbyte space becomes uncached and unmapped. Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual ckseg3 cksseg ckseg1 ckseg0 xkseg xkphys Address Error if SX=0 xksseg Address Error if UX=0 or ERL = 1 xkuseg
Memory Management 323 32-bit Kernel Mode, User Space (kuseg) In Kernel mode, when KX = 0 in the Status register, and the most-significant bit of the virtual address, A31, is cleared, the 32-bit kuseg virtual address space is selected; it covers the full 2 31 bytes (2 Gbytes) of the current user address space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. 32-bit Kernel Mode, Kernel Space 0 (kseg0) In Kernel mode, when KX = 0 in the Status register and the most-significant three bits of the virtual address are 100 2 , 32-bit kseg0 virtual address space is selected; it is the 2 29 -byte (512-Mbyte) kernel physical space. References to kseg0 are not mapped through the TLB; the physical address is selected by subtracting 0x8000 0000 from the virtual address. The K0 field of the Config register determines cacheability and coherency. 32-bit Kernel Mode, Kernel Space 1 (kseg1) In Kernel mode, when KX = 0 in the Status register and the most-significant three bits of the 32-bit virtual address are 101 2 , 32-bit kseg1 virtual address space is selected; it is the 2 29 -byte (512-Mbyte) kernel physical space. References to kseg1 are not mapped through the TLB; the physical address is selected by subtracting 0xA000 0000 from the virtual address. Caches are disabled for accesses to these addresses, and physical memory (or memory-mapped I/O device registers) are accessed directly. 32-bit Kernel Mode, Supervisor Space (ksseg) In Kernel mode, when KX = 0 in the Status register and the most-significant three bits of the 32-bit virtual address are 110 2 , the ksseg virtual address space is selected; it is the current 2 29 -byte (512-Mbyte) supervisor virtual space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. 32-bit Kernel Mode, Kernel Space 3 (kseg3) References to ksseg are mapped through the TLB. In Kernel mode, when KX = 0 in the Status register and the most-significant three bits of the 32-bit virtual address are 111 2 , the kseg3 virtual address space is selected; it is the current 2 29 -byte (512-Mbyte) kernel virtual space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. References to kseg3 are mapped through the TLB. MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Page 373 and 374: CPU Exceptions 343 TLB Invalid Exce
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Page 377 and 378: CPU Exceptions 347 Integer Overflow
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Page 387 and 388: CPU Exceptions 357 17.5 COP0 Instru
Page 389 and 390: 18. Cache Test Mode The R10000 proc
Page 391 and 392: Cache Test Mode 361 18.3 Entering C
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Page 395 and 396: Cache Test Mode 365 Auto-Increment
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Page 399 and 400: A. Glossary The following terms are
Page 401 and 402: A.6 Dynamic Scheduling The R10000 p
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A.11 Nonblocking Loads and Stores M
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A.13 Logical and Physical Registers
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Index I-1 Index Numerics 16-word, c
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Index I-3 uncached accelerated, des
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Index I-5 branch on CP0 instruction
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Index I-7 F fetch pipeline 6, 17 fe
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Index I-9 TLBWR 285, 300 unsupporte
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Index I-11 NMI see also nonmaskable
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Index I-13 CP0 (description of) 235
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Index I-15 SysAD[20:16] interrupt r
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Index I-17 SysWrRdy, signal 41, 118
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