MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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320 Chapter 16. Supervisor Mode Operations 0x FFFF FFFF 0x E000 0000 0x DFFF FFFF 0x C000 0000 0x BFFF FFFF 0x 8000 0000 0x 7FFF FFFF 0x 0000 0000 32-bit KSU = 01 and EXL = 0 and ERL = 0 and SX = 0 Address Error 0.5 Gbytes Mapped Address Error 2 Gbytes Mapped Supervisor mode is designed for layered operating systems in which a true kernel runs in processor Kernel mode, and the rest of the operating system runs in Supervisor mode. The processor operates in Supervisor mode when the Status register contains the Supervisor-mode bit-values shown in Table 16-1. 32-bit Supervisor Mode, User Space (suseg) Figure 16-2 shows Supervisor mode address mapping. sseg suseg 0x FFFF FFFF FFFF FFFF 0x FFFF FFFF E000 0000 0x FFFF FFFF DFFF FFFF 0x FFFF FFFF C000 0000 0x FFFF FFFF BFFF FFFF 0x 4000 1000 0000 0000 0x 4000 0FFF FFFF FFFF 0x 4000 0000 0000 0000 0x 3FFF FFFF FFFF FFFF 0x 0000 1000 0000 0000 0x 0000 0FFF FFFF FFFF 0x 0000 0000 8000 0000 0x 0000 0000 7FFF FFFF 0x 0000 0000 0000 0000 64-bit KSU = 01 and EXL = 0 and ERL = 0 and SX = 1 Address Error 0.5 Gbytes Mapped Address Error 16 Tbytes Mapped Address Error 16 Tbytes Mapped Figure 16-2 Supervisor Mode Address Space In Supervisor mode, when SX = 0 in the Status register and the most-significant bit of the 32-bit virtual address is set to 0, the suseg virtual address space is selected; it covers the full 2 31 bytes (2 Gbytes) of the current user address space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. This mapped space starts at virtual address 0x0000 0000 and runs through 0x7FFF FFFF. Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual csseg xsseg Address Error if UX=0 xsuseg
Memory Management 321 32-bit Supervisor Mode, Supervisor Space (sseg) In Supervisor mode, when SX = 0 in the Status register and the three mostsignificant bits of the 32-bit virtual address are 110 2 , the sseg virtual address space is selected; it covers 2 29 -bytes (512 Mbytes) of the current supervisor address space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. This mapped space begins at virtual address 0xC000 0000 and runs through 0xDFFF FFFF. 64-bit Supervisor Mode, User Space (xsuseg) In Supervisor mode, when SX = 1 in the Status register and bits 63:62 of the virtual address are set to 002 , selection of the xsuseg virtual address space is dependent upon the UX bit. • if UX = 1, the entire space from 0x0000 0000 0000 0000 through 0000 0FFF FFFF FFFF (16 Tbytes) is selected. • If UX = 0, the address space 0x0000 0000 0000 0000 through 0000 0000 7FFF FFFF (2 Gbytes) is selected. Addressing the space ranging from 0000 0000 8000 0000 through 0000 0FFF FFFF FFFF will cause an address error. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. 64-bit Supervisor Mode, Current Supervisor Space (xsseg) In Supervisor mode, when SX = 1 in the Status register and bits 63:62 of the virtual address are set to 01 2 , the xsseg current supervisor virtual address space is selected. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. This mapped space begins at virtual address 0x4000 0000 0000 0000 and runs through 0x4000 0FFF FFFF FFFF. 64-bit Supervisor Mode, Separate Supervisor Space (csseg) In Supervisor mode, when SX = 1 in the Status register and bits 63:62 of the virtual address are set to 11 2 , the csseg separate supervisor virtual address space is selected. Addressing of the csseg is compatible with addressing sseg in 32-bit mode. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. This mapped space begins at virtual address 0xFFFF FFFF C000 0000 and runs through 0xFFFF FFFF DFFF FFFF. MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Page 301 and 302: Coprocessor 0 271 Event 14 for Coun
Page 303 and 304: Coprocessor 0 273 14.21 ECC Registe
Page 305 and 306: Coprocessor 0 275 CacheErr Register
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Page 309 and 310: Coprocessor 0 279 Errata Primary In
Page 311 and 312: Coprocessor 0 281 Errata Errata Sec
Page 313 and 314: Coprocessor 0 283 Primary Data Cach
Page 315 and 316: Coprocessor 0 285 14.25 CP0 Instruc
Page 317 and 318: Coprocessor 0 287 14.27 CACHE Instr
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Page 325 and 326: Coprocessor 0 295 MTPS 31 Format: M
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Page 329 and 330: Coprocessor 0 299 14.36 TLBWI Instr
Page 331 and 332: 15. Floating-Point Unit This sectio
Page 333 and 334: Floating-Point Unit 303 15.2 Floati
Page 335 and 336: Floating-Point Unit 305 Load and St
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Page 343 and 344: Floating-Point Unit 313 Moves and C
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Page 347 and 348: Memory Management 317 Addressing Mo
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Page 353 and 354: Memory Management 323 32-bit Kernel
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Page 359 and 360: Memory Management 329 Using the TLB
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Page 367 and 368: CPU Exceptions 337 Soft † Reset E
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Page 371 and 372: CPU Exceptions 341 TLB Exceptions T
Page 373 and 374: CPU Exceptions 343 TLB Invalid Exce
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Page 377 and 378: CPU Exceptions 347 Integer Overflow
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Page 383 and 384: CPU Exceptions 353 Floating-Point E
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Page 387 and 388: CPU Exceptions 357 17.5 COP0 Instru
Page 389 and 390: 18. Cache Test Mode The R10000 proc
Page 391 and 392: Cache Test Mode 361 18.3 Entering C
Page 393 and 394: Cache Test Mode 363 18.5 SysAD(63:0
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Page 399 and 400: A. Glossary The following terms are
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A.6 Dynamic Scheduling The R10000 p
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A.11 Nonblocking Loads and Stores M
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A.13 Logical and Physical Registers
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Index I-1 Index Numerics 16-word, c
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Index I-3 uncached accelerated, des
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Index I-5 branch on CP0 instruction
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Index I-7 F fetch pipeline 6, 17 fe
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Index I-9 TLBWR 285, 300 unsupporte
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Index I-11 NMI see also nonmaskable
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Index I-13 CP0 (description of) 235
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Index I-15 SysAD[20:16] interrupt r
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Index I-17 SysWrRdy, signal 41, 118
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