MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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4 Chapter 1. 1.3 What is an R10000 Microprocessor? Errata The R10000 processor is a single-chip superscalar RISC microprocessor that is a follow-on to the MIPS RISC processor family that includes, chronologically, the R2000, R3000, R6000, R4400, and R8000. The R10000 processor uses the MIPS ANDES architecture, or Architecture with Nonsequential Dynamic Execution Scheduling. The R10000 processor has the following major features (terms in bold are defined in the Glossary): • it implements the 64-bit MIPS IV instruction set architecture (ISA) • it can decode four instructions each pipeline cycle, appending them to one of three instruction queues • it has five execution pipelines connected to separate internal integer and floating-point execution (or functional) units • it uses dynamic instruction scheduling and out-of-order execution • it uses speculative instruction issue (also termed “speculative branching”) • it uses a precise exception model (exceptions can be traced back to the instruction that caused them) • it uses non-blocking caches • it has separate on-chip 32-Kbyte primary instruction and data caches • it has individually-optimized secondary cache and System interface ports • it has an internal controller for the external secondary cache • it has an internal System interface controller with multiprocessor support The R10000 processor is implemented using 0.35-micron CMOS VLSI circuitry on a single 17 mm-by-18 mm chip that contains about 6.7 million transistors, including about 4.4 million transistors in its primary caches. Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
Introduction to the R10000 Processor 5 R10000 Superscalar Pipeline Stage 1 Fetch 5 Execution Pipelines Instruction Primary Instruction Cache Cache Stage 2 Decode FP Add Pipeline (FP Queue) FP Multiply Pipeline (FP Queue) Integer ALU Pipeline (Integer Queue) Integer ALU Pipeline (Integer Queue) Load/Store Pipeline (Address Queue) Instruction Fetch Pipeline Decode -------- Branch Unit 4 Instruction/Cycle Fetch and Decode The R10000 superscalar processor fetches and decodes four instructions in parallel each cycle (or pipeline stage). Each pipeline includes stages for fetching (stage 1 in Figure 1-4), decoding (stage 2) issuing instructions (stage 3), reading register operands (stage 3), executing instructions (stages 4 through 6), and storing results (stage 7). Stage 3 Issue Issue RF RF FAdd - - 1 FAdd - - 2 FAdd - - 3 Result Issue Issue RF RF Issue Issue RF RF ALU1 ALU1 Issue Issue RF RF ALU2 ALU2 Issue Issue RF RF Queues 7 Pipeline Stages Stage 4 Execute FMpy FMpy -1 -1 FMpy FMpy - - 2 2 FMpy FMpy - - 3 3 Result Result Addr.Calc . Addr.Calc . Stage 5 Execute Result Result Result Result Stage 6 Execute Data Data Cache Result Cache Result TLB TLB Read operands from Floating-Point or Integer Register Files Branch Address (one branch can be handled each cycle) Functional Units (Execute Instruction) Figure 1-4 Superscalar Pipeline Architecture in the R10000 Stage 7 Store Floating-Point Queue and Registers Integer Register Operands 2-way Interleaved Cache Translation-Lookaside Buffer MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
Page 1 and 2: MIPS R10000 Microprocessor User’s
Page 3 and 4: Acknowledgments This book represent
Page 5 and 6: About This Manual Glossary Stylisti
Page 7 and 8: Table of Contents vii Contents Ackn
Page 9 and 10: Table of Contents ix Superscalar In
Page 11 and 12: Table of Contents xi 3 Interface Si
Page 13 and 14: Table of Contents xiii 5 Secondary
Page 15 and 16: Table of Contents xv SysAD[63:0] Ad
Page 17 and 18: Table of Contents xvii 7 Clock Sign
Page 19 and 20: Table of Contents xix 9 Error Prote
Page 21 and 22: Table of Contents xxi 11 JTAG Inter
Page 23 and 24: Table of Contents xxiii 13 Packagin
Page 25 and 26: Table of Contents xxv Branch on Cop
Page 27 and 28: Table of Contents xxvii 16 Memory M
Page 29 and 30: Table of Contents xxix 18 A Cache T
Page 31 and 32: 1. Introduction to the R10000 Proce
Page 33: Introduction to the R10000 Processo
Page 37 and 38: Introduction to the R10000 Processo
Page 63 and 64: 2. System Configurations The R10000
Page 65 and 66: System Configurations 35 2.2 Multip
Page 67 and 68: 3. Interface Signal Descriptions Th
Page 69 and 70: Interface Signal Descriptions 39 3.
Page 75 and 76: 4. Cache Organization and Coherency
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Cache Organization and Coherency 55
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Cache Organization and Coherency 57
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Coprocessor 0 273 14.21 ECC Registe
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Coprocessor 0 275 CacheErr Register
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Coprocessor 0 277 CacheErr Register
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Coprocessor 0 279 Errata Primary In
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Coprocessor 0 281 Errata Errata Sec
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Coprocessor 0 283 Primary Data Cach
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Coprocessor 0 285 14.25 CP0 Instruc
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Coprocessor 0 287 14.27 CACHE Instr
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Coprocessor 0 289 Cache CACHE (cont
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Coprocessor 0 291 14.29 DMTC0 Instr
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Coprocessor 0 293 14.31 MFC0 Instru
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Coprocessor 0 295 MTPS 31 Format: M
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Coprocessor 0 297 14.34 TLBP Instru
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Coprocessor 0 299 14.36 TLBWI Instr
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15. Floating-Point Unit This sectio
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Floating-Point Unit 303 15.2 Floati
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Floating-Point Unit 305 Load and St
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Floating-Point Unit 307 63 63 Doubl
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Floating-Point Unit 309 Floating-Po
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Floating-Point Unit 311 Loading the
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Floating-Point Unit 313 Moves and C
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16. Memory Management This section
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Memory Management 317 Addressing Mo
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Memory Management 319 32-bit User M
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Memory Management 321 32-bit Superv
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Memory Management 323 32-bit Kernel
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Memory Management 325 0X BFFFFFFF 0
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Memory Management 327 64-bit Virtua
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Memory Management 329 Using the TLB
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17. CPU Exceptions This chapter des
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CPU Exceptions 333 17.3 TLB Refill
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CPU Exceptions 335 Priority of Exce
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CPU Exceptions 337 Soft † Reset E
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CPU Exceptions 339 NMI Exception Ca
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CPU Exceptions 341 TLB Exceptions T
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CPU Exceptions 343 TLB Invalid Exce
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CPU Exceptions 345 Cache Error Exce
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CPU Exceptions 347 Integer Overflow
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CPU Exceptions 349 System Call Exce
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CPU Exceptions 351 Reserved Instruc
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CPU Exceptions 353 Floating-Point E
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CPU Exceptions 355 Interrupt Except
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CPU Exceptions 357 17.5 COP0 Instru
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18. Cache Test Mode The R10000 proc
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Cache Test Mode 361 18.3 Entering C
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Cache Test Mode 363 18.5 SysAD(63:0
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Cache Test Mode 365 Auto-Increment
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Cache Test Mode 367 Auto-Increment
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A. Glossary The following terms are
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A.6 Dynamic Scheduling The R10000 p
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A.11 Nonblocking Loads and Stores M
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A.13 Logical and Physical Registers
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Index I-1 Index Numerics 16-word, c
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Index I-3 uncached accelerated, des
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Index I-5 branch on CP0 instruction
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Index I-7 F fetch pipeline 6, 17 fe
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Index I-9 TLBWR 285, 300 unsupporte
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Index I-11 NMI see also nonmaskable
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Index I-13 CP0 (description of) 235
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Index I-15 SysAD[20:16] interrupt r
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Index I-17 SysWrRdy, signal 41, 118
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