MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Floating-Point Unit 305
Load and Store Operations
31
0
Memory †
Singleword Load/Store when Register is Even
LWC1 ft,address (MTC1 ft,rs)
When FR = 0, floating-point load and stores operate as follows:
• A doubleword load or store is handled the same as if the FR bit was
set to 1, as long as the register selected is even (0, 2, 4, etc.).
• If the register selected is odd, the load/store is invalid.
These operations are shown in Figure 15-3. Singleword loads/stores to even and
odd registers are also shown.
63 32 31
0
Unchanged Load 32-bit
SWC1 ft,address (MFC1 rt,fs)
63
32
Sign extend reg.
31
Memory †
†
Move to/from selects an integer register instead.
Moved 32-bit data is sign-extended in 64-bit register.
FR=0 16-Register Mode
Doubleword Load/Store
Same as FR=1 if register is even, else invalid.
31
0
Memory †
Singleword Load/Store when Register is Odd
LWC1 ft,address
63 32 31
0
Load 32-bit Unchanged
SWC1 ft,address
63
32
Sign extend reg.
Figure 15-3 Loading and Storing Floating-Point Registers in 16-Register Mode
NOTE: Move (MOV) and conditional move (MOVC, MOVN, MOVZ are
included in these arithmetic operations, although no arithmetic is actually
performed.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
0
31
(MTC1 ft,rs)
(MFC1 rt,fs)
Memory †
†
Move to/from selects an integer register instead.
Moved 32-bit data is sign-extended in 64-bit register.
0