MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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300 Chapter 14. 14.37 TLBWR Instruction TLBWR 31 26 25 24 Format: TLBWR Description: Operation: Exceptions: The G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and EntryLo1 registers. The TLB entry pointed at by the contents of the TLB Random register is loaded with the contents of the EntryHi and EntryLo registers. In the R4400, this instruction had to be executed in unmapped spaces, and in the R10000 processor it can be executed in unmapped spaces without any hazard. There is no hazard to executing a TLB write in mapped space unless the write affects those instructions that have been fetched and buffered by the processor. If necessary, a flush to the instruction-fetch pipeline, such as execution of a jump register instruction, after a TLB write can avoid this hazard. In the R4400 processor, a TLB write instruction is used to write the whole page frame number from the EntryLo registers to the TLB entry. Depending on the page size specified in the corresponding PageMask register, the lower bits of PFN may not be used for address translation. In the R10000 processor, the lower bits not used for address translation are forced to zeroes during a TLB write. This does not affect TLB address translation, however a TLB read may not retrieve what was originally written. Coprocessor unusable exception Write Random TLB Entry COP0 0 1 0 0 0 0 CO 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLBWR 0 0 0 1 1 0 6 1 19 6 32, 64T: TLB[Random5...0 ] ← PageMask || (EntryHi and not PageMask) || EntryLo1 || EntryLo0 Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual TLBWR 6 5 0
15. Floating-Point Unit This section describes the operation of the FPU, including the register definitions. The Floating-Point unit consists of the following functional units: • add unit • multiply unit • divide unit • square-root unit The add unit performs floating-point add and subtract, compare, and conversion operations. Except for Convert Integer To Single-Precision (float), all operations have a 2-cycle latency and a 1-cycle repeat rate. The multiply unit performs single-precision or double-precision multiplication with a 2-cycle latency and a 1-cycle repeat rate. The divide and square-root units do single- or double-precision operations. They have long latencies and low repeat rates (20 to 40 cycles). MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997301
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
Page 279 and 280: Coprocessor 0 249 Diagnostic Status
Page 281 and 282: Coprocessor 0 251 Coprocessor Acces
Page 283 and 284: Coprocessor 0 253 Table 14-13 Cause
Page 285 and 286: Coprocessor 0 255 14.13 Processor R
Page 287 and 288: Coprocessor 0 257 14.15 Load Linked
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Page 291 and 292: Coprocessor 0 261 14.19 Diagnostic
Page 293 and 294: Coprocessor 0 263 Errata There are
Page 295 and 296: Coprocessor 0 265 Errata Errata The
Page 297 and 298: Coprocessor 0 267 Event 1 for Count
Page 299 and 300: Coprocessor 0 269 Event 6 for Count
Page 301 and 302: Coprocessor 0 271 Event 14 for Coun
Page 303 and 304: Coprocessor 0 273 14.21 ECC Registe
Page 305 and 306: Coprocessor 0 275 CacheErr Register
Page 307 and 308: Coprocessor 0 277 CacheErr Register
Page 309 and 310: Coprocessor 0 279 Errata Primary In
Page 311 and 312: Coprocessor 0 281 Errata Errata Sec
Page 313 and 314: Coprocessor 0 283 Primary Data Cach
Page 315 and 316: Coprocessor 0 285 14.25 CP0 Instruc
Page 317 and 318: Coprocessor 0 287 14.27 CACHE Instr
Page 319 and 320: Coprocessor 0 289 Cache CACHE (cont
Page 321 and 322: Coprocessor 0 291 14.29 DMTC0 Instr
Page 323 and 324: Coprocessor 0 293 14.31 MFC0 Instru
Page 325 and 326: Coprocessor 0 295 MTPS 31 Format: M
Page 327 and 328: Coprocessor 0 297 14.34 TLBP Instru
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Page 357 and 358: Memory Management 327 64-bit Virtua
Page 359 and 360: Memory Management 329 Using the TLB
Page 361 and 362: 17. CPU Exceptions This chapter des
Page 363 and 364: CPU Exceptions 333 17.3 TLB Refill
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Page 367 and 368: CPU Exceptions 337 Soft † Reset E
Page 369 and 370: CPU Exceptions 339 NMI Exception Ca
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Page 373 and 374: CPU Exceptions 343 TLB Invalid Exce
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Page 377 and 378: CPU Exceptions 347 Integer Overflow
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CPU Exceptions 351 Reserved Instruc
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CPU Exceptions 353 Floating-Point E
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CPU Exceptions 355 Interrupt Except
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CPU Exceptions 357 17.5 COP0 Instru
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18. Cache Test Mode The R10000 proc
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Cache Test Mode 361 18.3 Entering C
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Cache Test Mode 363 18.5 SysAD(63:0
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Cache Test Mode 365 Auto-Increment
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Cache Test Mode 367 Auto-Increment
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A. Glossary The following terms are
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A.6 Dynamic Scheduling The R10000 p
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A.11 Nonblocking Loads and Stores M
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A.13 Logical and Physical Registers
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Index I-1 Index Numerics 16-word, c
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Index I-3 uncached accelerated, des
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Index I-5 branch on CP0 instruction
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Index I-7 F fetch pipeline 6, 17 fe
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Index I-9 TLBWR 285, 300 unsupporte
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Index I-11 NMI see also nonmaskable
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Index I-13 CP0 (description of) 235
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Index I-15 SysAD[20:16] interrupt r
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Index I-17 SysWrRdy, signal 41, 118
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