MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

300 Chapter 14.
14.37 TLBWR Instruction
TLBWR
31 26 25 24
Format: TLBWR
Description:
Operation:
Exceptions:
The G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and
EntryLo1 registers.
The TLB entry pointed at by the contents of the TLB Random register is loaded with the
contents of the EntryHi and EntryLo registers.
In the R4400, this instruction had to be executed in unmapped spaces, and in the
R10000 processor it can be executed in unmapped spaces without any hazard.
There is no hazard to executing a TLB write in mapped space unless the write affects
those instructions that have been fetched and buffered by the processor. If necessary,
a flush to the instruction-fetch pipeline, such as execution of a jump register
instruction, after a TLB write can avoid this hazard.
In the R4400 processor, a TLB write instruction is used to write the whole page frame
number from the EntryLo registers to the TLB entry. Depending on the page size
specified in the corresponding PageMask register, the lower bits of PFN may not be
used for address translation. In the R10000 processor, the lower bits not used for
address translation are forced to zeroes during a TLB write. This does not affect TLB
address translation, however a TLB read may not retrieve what was originally written.
Coprocessor unusable exception
Write Random TLB Entry
COP0
0 1 0 0 0 0
CO
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TLBWR
0 0 0 1 1 0
6
1
19
6
32, 64T: TLB[Random5...0 ] ←
PageMask || (EntryHi and not PageMask) || EntryLo1 || EntryLo0
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
TLBWR
6 5
0