MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Coprocessor 0 297
14.34 TLBP Instruction
TLBP
31 26 25 24
Format: TLBP
Description:
Operation:
Exceptions:
Probe TLB For Matching Entry
The Index register is loaded with the address of the TLB entry whose contents match
the contents of the EntryHi register. If no TLB entry matches, the high-order bit of the
Index register is set to 0x80000000, as it is in the R4400 processor.
The architecture does not specify the operation of memory references associated with
the instruction immediately after a TLBP instruction, nor is the operation specified if
more than one TLB entry matches.
Coprocessor unusable exception
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
TLBP
COP0
0 1 0 0 0 0
CO
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TLBP
0 0 1 0 0 0
6
1
19
6
32 T: Index← 1 || 025 || undefined6 for i in 0...TLBEntries–1
if (TLB[i] 95...77 = EntryHi31...12) and (TLB[i] 76 or
(TLB[i] 71...64 = EntryHi7...0 )) then
Index ← 026 || i 5...0
endif
endfor
64 T: Index← 1 || 0 25 || undefined6 for i in 0...TLBEntries–1
if (TLB[i] 171...141 and not (015 || TLB[i] 216...205 ))
= EntryHi43...13 ) and not (015 || TLB[i] 216...205 )) and
(TLB[i] 140 or (TLB[i] 135...128 = EntryHi7...0 )) then
Index ← 026 || i 5...0
endif
endfor
6 5
0