MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

292 Chapter 14.
14.30 ERET Instruction
ERET
31 26 25 24
Format: ERET
Description:
Operation:
Exceptions:
ERET is the R10000 instruction for returning from an interrupt, exception, or error trap.
Unlike a branch or jump instruction, ERET does not execute the next instruction.
ERET must not itself be placed in a branch delay slot.
If the processor is servicing an error trap (SR 2 = 1), then load the PC from the ErrorEPC
and clear the ERL bit of the Status register (SR 2 ). Otherwise (SR 2 = 0), load the PC from
the EPC, and clear the EXL bit of the Status register (SR 1 ).
An ERET executed between a LL and SC also causes the SC to fail.
If there is no exception (EXL=0 and ERL=0 in the Status register), execution of an ERET
instruction is meaningless.
Execution of an ERET when ERL=0, regardless of the state of EXL, sets EXL to 0 and a
jump is taken to the address presently held in the EPC register, even when there is no
exception.
Coprocessor unusable exception
Exception Return
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
ERET
COP0
0 1 0 0 0 0
CO
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ERET
0 1 1 0 0 0
6
1
19
6
32, 64 T: if SR 2 = 1 then
PC ← ErrorEPC
SR ← SR 31...3 || 0 || SR 1...0
else
PC ← EPC
SR ← SR 31...2 || 0 || SR 0
endif
LLbit ← 0
6 5
0