MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

290 Chapter 14.
14.28 DMFC0 Instruction
DMFC0
Format: DMFC0 rt, rd
Description:
Operation:
Exceptions:
Doubleword Move From
System Control Coprocessor
31 26 25 21 20 16 15 11 10
0
COP0
0 1 0 0 0 0
DMF
0 0 0 0 1
rt rd
0
0 0 0 0 0 0 0 0 0 00
6 5 5 5
11
The contents of coprocessor register rd of the CP0 are loaded into general register rt.
This operation is defined for the R10000 operating in 64-bit mode and in 32-bit kernel
mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved
instruction exception. All 64-bits of the general register destination are written from
the coprocessor register source. The operation of DMFC0 on a 32-bit coprocessor 0
register is undefined.
64 T: data ← CPR[0,rd]
T+1: GPR[rt] ← data
Coprocessor unusable exception
Reserved instruction exception (R10000 in 32-bit user mode
R10000 in 32-bit supervisor mode)
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
DMFC0