MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

288 Chapter 14.
Cache
CACHE (continued) CACHE
Fill, Create Dirty, Hit WriteBack and Hit Set Virtual are not supported in the R10000
processor.
The R10000 processor adds two new CacheOps: Index Load Data (110 2 ) and Index Store
Data (111 2). These changes are also reflected in the CP0 TagHi, TagLo and ECC registers.
The primary instruction and data caches have a block size of 16 words and 32 bytes (8
data words), respectively.
NOTE: A 32-bit instruction is predecoded into a 36-bit instruction word before
entering the primary instruction cache. The instruction fetch addresses remain the
same and are not affected by the predecode.
The secondary cache, a unified cache, has a block size of either 64 or 128 bytes,
configurated during reset. For a cache of 2 CACHESIZE bytes with 2 BLOCKSIZE bytes per
tag,
VACACHESIZE-2..BLOCKSIZE specifies the block for the primary cache, and
PACACHESIZE-2..BLOCKSIZE specifies the block for the secondary cache.
For the Index CacheOps, address bit 0 is used to specify the way, 0 or 1, for the
CacheOp. For this reason, bit 0 is not checked for alignment-type Address Error
exception for the Index CacheOps. For CacheOps that access data in caches,
VABLOCKSIZE-1..2 specifies a word within a block for primary caches, and
PABLOCKSIZE-1..3 specifies a doubleword in the secondary cache.
A cache hit accesses the specified cache as normal data references, and performs the
specified operation if the cache block contains valid data at the specified physical
address. If the cache line is invalid or contains a differing physical address (a cache
miss), no operation is performed. Since the R10000 processor uses 2-way set associative
caches, the Hit operation performs tag comparison in both ways of the cache. No index
needs to be provided for such CacheOps. If both ways register a hit, the execution of
the CacheOp is undefined.
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual