MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Coprocessor 0 285
14.25 CP0 Instructions
Hazards
Branch on Coprocessor 0
Table 14-25 lists the CP0 instructions defined for the R10000 processor. Since they
are implementation dependent, they are included here and not in the MIPS ISA
manual.
Table 14-25 CP0 Instructions
OpCode Description ISA
CACHE Cache Operation III
DMFC0 Doubleword Move From CP0 III
DMTC0 Doubleword Move To CP0 III
ERET Exception Return III
MFC0 Move from CP0 I
MTC0 Move to CP0 I
TLBP Probe TLB for Matching Entry I
TLBR Read Indexed TLB Entry I
TLBWI Write Indexed TLB Entry I
TLBWR Write Random TLB Entry I
The processor detects most of the pipeline hazards in hardware, including CP0
hazards and load hazards. No NOP instructions are required to correct
instruction sequences.
On the R4400 processor, CacheOps that hit in the specified cache set the CH bit in
the Diagnostic field of the CP0 Status register (bit 18). Though it was
undocumented, this bit could be tested by the Branch on Coprocessor 0 instructions
(bc0t, bc0f, bc0tl, bc0fl).
The R10000 processor also implements the CH bit but it is not associated with a
Coprocessor 0 condition. Instead, execution of a branch on Coprocessor 0
instruction takes a Reserved Instruction exception.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997