MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

282 Chapter 14.
CacheOp is Index Load/Store Data
Errata
Primary Instruction Cache Operation
This section describes the following three states of the TagLo and TagHi registers,
when the CacheOp is an Index Load/Store Data:
• primary instruction cache operation
• primary data cache operation
• secondary cache operation
If the CacheOp is an Index Load/Store Data for the primary instruction cache, the
TagHi register stores the most significant four bits of a 36-bit instruction, as shown
in Figure 14-31; the rest of the instruction is stored in the TagLo register.
31
31
Figure 14-31 TagHi/Lo Register Fields in Primary Instruction Cache
When CacheOp is Index Load/Store Data
0: Reserved. Must be written as zeroes, and returns zeroes when read.
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
0
28
Inst[31:0]
32
4 3
Inst[35:32]
4
0
0
TagLo
TagHi