MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Coprocessor 0 281
Errata
Errata
Secondary Cache Operation
If the CacheOp is an Index Load/Store Tag for secondary cache operations, the fields
of the TagHi and TagLo registers are defined as follows:
STag0: contains physical address bits [35:18] stored in the cache tag
SState: contains the secondary cache state of the line, as follows:
002 = Invalid
01 2 = Shared
10 2 = Clean Exclusive
11 2 = Dirty Exclusive
VIndex (virtual index): contains only two bits of significance since the32 Kbyte 2way
set associative primary caches are addressed using only two untranslated
address bits (VA[13:12]) plus the offset within the virtual page.
ECC: contains the ECC for the STag, SState and VIndex fields.
MRU: indicates which way was the most recently used in the set.
STag1: contains the physical address bits [39:36] stored in the cache tag.
0: Reserved. Must be written as zeroes, and returns zeroes when read.
Figure 14-30 shows the fields of the TagHi and TagLo registers.
31
31
MRU
1
STag0
30
Figure 14-30 TagHi/Lo Register Fields in Secondary Cache
When CacheOp is Index Load/Store Tag
Figure 14-30, size of the STag0 field is revised.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
18
14 13 1211
0
2
SState
2
0
27
10
9
0
1
8
VIndex
2
7 6
ECC
7
4 3
STag1
4
0
0
TagLo
TagHi