MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

280 Chapter 14.
Errata
PTag0: contains physical address bits [35:12] stored in the cache tag
PState: together with the Refill bit of the State Modifier in the TagHi register, PState
determines the state of the cache block in the primary data cache, as shown in
Table 14-24.
Table 14-24 PState Field Definition in TagHi/Lo Registers, For Primary Data Cache Operation
When CacheOp is Index Load/Store Tag
PState Refill=0 Refill=1
002 Invalid Refill clean (block is being
refilled)
012 Shared
Upgrade Share (converting
shared to dirty)
102 Clean Upgrade Clean
Exclusive (converting clean to dirty).
Dirty Refill dirty (block is being
112 Exclusive refilled for a store)
LRU: indicates which way is the least recently used of the set.
SP: state even parity bit for the PState field and the Way bit
Way: indicates which secondary cache set contains the primary cache line for this
tag
TP: tag even parity bit.
0: Reserved. Must be written as zeroes, and returns zeroes when read.
Figure 14-29 shows the fields of the TagHi and TagLo registers.
31
31
State
Modifier
3
29
28
PTag0
Figure 14-29 TagHi/Lo Register Fields in Primary Data Cache
When CacheOp is Index Load/Store Tag
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
24
8 7
0
25
PState
2
6
0
2
4
3
3
2
LRU SP
Way
PTag1
4
1
TP
1 1 1 1
0
0
TagLo
TagHi