MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

278 Chapter 14.
14.23 TagLo (28) and TagHi (29) Registers
CacheOp is Index Load/Store Tag
The TagHi and TagLo registers are 32-bit read/write registers used to hold the
following: †
• the primary cache tag and parity
• the secondary cache tag and ECC
• the data in primary or secondary caches for certain CacheOps
TagHi/Lo formats in the R10000 processor differ from those in the R4400 due to
changes in CacheOps and cache architecture. R10000 formats depend on the type
of CacheOp executed and the cache to which it is applied. The reserved fields are
read as zeroes after executing an Index Load Tag or an Index Load Data CacheOp and
ignored when executing an Index Store Tag or an Index Store Data CacheOp.
To ensure NT kernel compatibility, the TagLo register is implemented as a 32-bit
read/write register. The value written by an MTC0 instruction can be retrieved by
a MFC0 instruction, unless an intervening CACHE instruction has modified the
content.
This section gives the TagLo and TagHi register formats for the following
CacheOp and cache combinations:
• CacheOp is Index Load/Store Tag
- primary instruction cache operation
- primary data cache operation
- secondary cache operation
• CacheOp is Index Load/Store Data
- primary instruction cache operation
- primary data cache operation
- secondary cache operation
This section describes the three states of the TagLo and TagHi registers, when the
CacheOp is an Index Load/Store Tag for the following operations:
• primary instruction cache operation
• primary data cache operation
• secondary cache operation
† To ensure NT kernel compatibility, the TagLo register is implemented as a 32-bit
read/write register. The value written by a MTC0 instruction can be retrieved by a
MFC0 instruction, unless intervening CACHE instructions modify the content.
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual