MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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276 Chapter 14. CacheErr Register Format for Secondary Cache Errors Errata Figure 14-26 shows the format of the CacheErr register when a secondary cache error occurs. 31 10 2 30 29 EW 1 28 0 1 27 26 25 24 23 Figure 14-26 CacheErr Register Format for Secondary Cache Errors EW: set when CacheErr register is already holding the values of a previous error D: uncorrectable data array error (way1 || way0) TA: uncorrectable tag array error (way1 || way0) SIdx: secondary cache physical block index (PA[22:6] for 16-word block size or PA[22:7] for 32-word block size) 0: Reserved. Must be written as zeroes, and returns zeroes when read. Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual D 2 TA 2 0 1 22 SIdx 17 6 6 5 0 0
Coprocessor 0 277 CacheErr Register Format for System Interface Errors Errata Figure 14-27 shows the format of the CacheErr register when a System interface error occurs. 31 11 2 30 29 EW 1 28 EE Figure 14-27 CacheErr Register Format for System Interface Errors EW: set when CacheErr register is already holding the values of a previous error EE: data error on a CleanExclusive or DirtyExclusive D: uncorrectable system block data response error (way1 || way0) SA: uncorrectable system address bus error SC: uncorrectable system command bus error SR: uncorrectable system response bus error SIdx: secondary cache physical block index 0: Reserved. Must be written as zeroes, and returns zeroes when read. MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997 1 27 26 D 2 25 SA 1 24 23 SC 1 SR 1 22 SIdx 17 6 5 0 6 0
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
Page 255 and 256: Packaging 225 Table 13-3 (cont.) Si
Page 261 and 262: Packaging 231 Figure 13-3 599LGA PW
Page 263 and 264: Packaging 233 Figure 13-5 599LGA Bo
Page 265 and 266: 14. Coprocessor 0 This chapter desc
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Page 269 and 270: Coprocessor 0 239 14.3 EntryLo0 (2)
Page 271 and 272: Coprocessor 0 241 14.4 Context (4)
Page 273 and 274: Coprocessor 0 243 14.6 Wired Regist
Page 275 and 276: Coprocessor 0 245 14.9 EntryHi Regi
Page 277 and 278: Coprocessor 0 247 CU2 CU2 CU1 CU1 C
Page 279 and 280: Coprocessor 0 249 Diagnostic Status
Page 281 and 282: Coprocessor 0 251 Coprocessor Acces
Page 283 and 284: Coprocessor 0 253 Table 14-13 Cause
Page 285 and 286: Coprocessor 0 255 14.13 Processor R
Page 287 and 288: Coprocessor 0 257 14.15 Load Linked
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Page 291 and 292: Coprocessor 0 261 14.19 Diagnostic
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Page 297 and 298: Coprocessor 0 267 Event 1 for Count
Page 299 and 300: Coprocessor 0 269 Event 6 for Count
Page 301 and 302: Coprocessor 0 271 Event 14 for Coun
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Page 311 and 312: Coprocessor 0 281 Errata Errata Sec
Page 313 and 314: Coprocessor 0 283 Primary Data Cach
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Page 317 and 318: Coprocessor 0 287 14.27 CACHE Instr
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Page 321 and 322: Coprocessor 0 291 14.29 DMTC0 Instr
Page 323 and 324: Coprocessor 0 293 14.31 MFC0 Instru
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Page 333 and 334: Floating-Point Unit 303 15.2 Floati
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Page 341 and 342: Floating-Point Unit 311 Loading the
Page 343 and 344: Floating-Point Unit 313 Moves and C
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Page 347 and 348: Memory Management 317 Addressing Mo
Page 349 and 350: Memory Management 319 32-bit User M
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Memory Management 327 64-bit Virtua
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Memory Management 329 Using the TLB
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17. CPU Exceptions This chapter des
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CPU Exceptions 333 17.3 TLB Refill
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CPU Exceptions 335 Priority of Exce
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CPU Exceptions 337 Soft † Reset E
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CPU Exceptions 339 NMI Exception Ca
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CPU Exceptions 341 TLB Exceptions T
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CPU Exceptions 343 TLB Invalid Exce
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CPU Exceptions 345 Cache Error Exce
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CPU Exceptions 347 Integer Overflow
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CPU Exceptions 349 System Call Exce
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CPU Exceptions 351 Reserved Instruc
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CPU Exceptions 353 Floating-Point E
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CPU Exceptions 355 Interrupt Except
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CPU Exceptions 357 17.5 COP0 Instru
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18. Cache Test Mode The R10000 proc
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Cache Test Mode 361 18.3 Entering C
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Cache Test Mode 363 18.5 SysAD(63:0
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Cache Test Mode 365 Auto-Increment
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Cache Test Mode 367 Auto-Increment
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A. Glossary The following terms are
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A.6 Dynamic Scheduling The R10000 p
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A.11 Nonblocking Loads and Stores M
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A.13 Logical and Physical Registers
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Index I-1 Index Numerics 16-word, c
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Index I-3 uncached accelerated, des
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Index I-5 branch on CP0 instruction
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Index I-7 F fetch pipeline 6, 17 fe
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Index I-9 TLBWR 285, 300 unsupporte
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Index I-11 NMI see also nonmaskable
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Index I-13 CP0 (description of) 235
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Index I-15 SysAD[20:16] interrupt r
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Index I-17 SysWrRdy, signal 41, 118
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