MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Coprocessor 0 271
Event 14 for Counter 0: Functional Unit Completion Cycles
This counter is incremented once on the cycle after at least one of the functional
units — ALU1, ALU2, FPU1, or FPU2 — marks an instruction as done.
Event 14 for Counter 1: Stores, or Prefetches with Store Hint to Clean Exclusive Secondary
Cache Blocks.
This counter is incremented on the cycle after a request to change the Clean
Exclusive state of the targeted secondary cache line to Dirty Exclusive is sent to the
SCTP logic.
Event 15 for Counter 0: Instruction Graduation.
This counter is incremented by the number of instructions that were graduated on
the previous cycle. When an integer multiply or divide instruction graduates, it is
counted as two graduated instructions.
Event 15 for Counter 1: Stores or Prefetches with Store Hint to Shared Secondary Cache
Blocks.
This counter is incremented on the cycle after a request to change the Shared state
of the targeted secondary cache line to Dirty Exclusive is sent to the SCTP logic.
The performance counters and associated control registers are written by using an
MTC0 instruction, as shown in Table 14-19.
Table 14-19 Writing Performance Registers Using MTC0
Opcode[15:11] Opcode[1:0] Operation
11001 00 Move to Performance Control 0
11001 01 Move to Performance Counter 0
11001 10 Move to Performance Control 1
11001 11 Move to Performance Counter 1
The performance counters and associated control registers are read by using a
MFC0 instruction, as shown in Table 14-20.
Table 14-20 Reading Performance Registers Using MFC0
Opcode[15:11] Opcode[1:0] Operation
11001 00 Move from Performance Control 0
11001 01 Move from Performance Counter 0
11001 10 Move from Performance Control 1
11001 11 Move from Performance Counter 1
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997