MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Coprocessor 0 267
Event 1 for Counter 0: Instructions Issued
The counter is incremented on each cycle by the sum of the three following events:
• Integer operations marked as done on the cycle. 0, 1 or 2 such
operations can be marked on each cycle. Since these operations (all
except for MUL and DIV) are marked done on the cycle following their
being issued to a functional unit, this number is nearly identical to the
number issued. The only difference is that re-issues are not counted.
• Floating point operations marked done in the active list. Possible values
are 0, 1 or 2. Since these operations take more than one cycle to
complete, it is possible for an instruction to be issued and then aborted
before it is counted, due to a branch-misprediction or exception
rollback.
• Load/store instructions first issued to the address calculation unit on
the previous cycle. Possible values are 0 or 1. Prefetch instructions are
counted as issued. Load/store instructions are counted as being issued
only once, even though they may have been issued more than one
time. † Any instruction which does not go to the load/store unit,
integer functional unit, or FP functional is counted. Some of those not
counted are: nops, bc1{f,t,fl,tl}, break, syscall, j, jal, jr, jalr, cp0
instructions.
Event 1 for Counter 1: Instruction Graduation.
The counter is incremented by the number of instructions that were graduated on
the previous cycle. When an integer multiply or divide instruction graduates, it is
counted as two instructions.
Event 2 for Counter 0: Load/Prefetch/Sync/CacheOp Issue.
Each of these instructions are counted as they are issued. A load instruction is
only counted once, even though it may have been issued more than one
time. †
Event 2 for Counter 1: Load/Prefetch/Sync/CacheOp Graduation.
Each of these instructions are counted as they are graduated. Up to four loads can
graduate in one cycle.
† This could be a result of DCache Tag being busy or four Instruction or Data cache
misses already present and waiting to be processed in the Secondary Cache
Transaction Processing (SCTP) logic.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997