MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

266 Chapter 14.
Errata
• 0: Reserved. Must be written as zeroes, and returns zeroes when read.
These modes can be set individually; for example, one could set all four bits to
count a certain event in all processor modes except during a cache error exception.
In describing the rules that are applied for the counting of each events listed in
Table 14-18, following terminology is used:
Done is defined as the point at which the instruction is successfully executed
by the functional unit but is not yet graduated.
Graduated is defined as the point in time when the instruction is successfully
executed (done), and it is the oldest instruction.
Secondary Cache Transaction Processing (SCTP) logic is on-chip logic in which up
to four internally-generated and one-externally generated secondary cache
transactions are queued to be processed.
The following rules apply for the counting of each event listed in Table 14-16:
Event 0 for Counter 0 and Counter 1: Cycles
The counter is incremented on each PClk cycle.
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual