MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Coprocessor 0 265
Errata
Errata
The fields of the Control register are:
• The Event field specifies the event to be counted, listed in Table 14-18.
Table 14-18 Counter Events
Event Counter 0 Counter 1
0 Cycles Cycles
1 Instructions issued Instructions graduated
2 Load/prefetch/sync/CacheOp issued Load/prefetch/sync/CacheOp graduated
3 Stores (including store-conditional) issued Stores (including store-conditional) graduated
4 Store conditional issued Store conditional graduated
5 Failed store conditional Floating-point instructions graduated
6 Branches resolved
Quadwords written back from primary data
cache
7 Quadwords written back from secondary cache TLB refill exceptions
8 Correctable ECC errors on secondary cache data Branches mispredicted
9 Instruction cache misses
Secondary cache load/store and cache-ops
operations
10 Secondary cache misses (instruction) Secondary cache misses (data)
11 Secondary cache way mispredicted (instruction) Secondary cache way mispredicted (data)
12 External intervention requests
13 External invalidate requests
14 Functional unit completion cycles
15 Instructions graduated
Made various changes to Table 14-18, as indicated by the underlines. Note that the
updated material reflects the functionality of silicon revision 3.0 and later. The status of
earlier silicon revisions are documented as silicon errata available on www.mips.com.
• The IE bit enables the assertion of IP[7] when the associated counter
overflows.
• The U, S, K, and EXL bits indicate the processor modes in which the
event is counted: U is user mode; S is supervisor mode; K is kernel
mode when EXL and ERL both are set to 0; the system is in kernel
mode and handling an exception when EXL is set to 1, as shown in
Table 14-22.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
External intervention request is determined to
have hit in secondary cache
External invalidate request is determined to
have hit in secondary cache
Stores or prefetches with store hint to
CleanExclusive secondary cache blocks
Stores or prefetches with store hint to Shared
secondary cache blocks