MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

264 Chapter 14.
14.20 Performance Counter Registers (25)
The R10000 processor defines two performance counters and two associated
control registers, which are mapped into CP0 register 25. An encoding in the
MTC0/MFC0 instructions on register 25 indicates which counter or control
register is used.
Each counter is a 32-bit read/write register and is incremented by one each time
the countable event, specified in its associated control register, occurs. Each
counter can independently count one type of event at a time.
The counter asserts an interrupt, IP[7], when its most significant bit (bit 31)
becomes one (the counter overflows) and the associated performance control
register enables the interrupt.
The counting continues after counter overflow whether or not an interrupt is
signalled.
The format of the control registers are shown in Figure 14-22.
31
Figure 14-22 Control Register Format
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
0
23
9
8 5 4 3 2
Event
4
IE
1
U
S
1
K
1 1 1 1
0
EXL