MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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260 Chapter 14. 14.18 FrameMask Register (21) The FrameMask register is new with the R10000 processor. It masks bits of the EntryLo0 and EntryLo1 registers so that these masked bits are not passed to the TLB while doing a TLB write (either TLBWI or TLBWR). A zero in the FrameMask register allows its corresponding bit in the EntryLo[1,0] registers to pass to the TLB; a one in the FrameMask register masks off its corresponding bit in the EntryLo registers and passes a zero to the TLB. Bits 15:0 of the FrameMask register control bits 33:18 of the EntryLo registers. The remaining bits of this register are ignored on write and read as zeroes. The content of this register is set to zero after a processor reset or a power-up event. Figure 14-20 shows the FrameMask register format. 31 FrameMask Register 0 0 Mask bits, PA[39:24] Figure 14-20 FrameMask Register Format Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual 16 16 16 15 0
Coprocessor 0 261 14.19 Diagnostic Register (22) Errata CP0 register 22, the Diagnostic register, is a new 64-bit register for processorspecific diagnostic functions. (Since this register is designed for local use, the diagnostic functions are subject to change without notice.) Currently, this register helps test the ITLB, branch caches, and the branch prediction scheme. In addition, it provides choices for branch prediction algorithms, to help diagnostic program writing. The twelve fields of the Diagnostic register, shown in Figure 14-21, are described below. All fields are read-only (all writes are ignored). ITLBM: this field is a 4-bit read-only counter. This field is incremented by one for each ITLB miss, and any overflow is ignored. Its value is undefined during reset, and its value is meaningless when used in an unmapped space. BSIdx: this field defines the entry in the branch stack to be used for the latest conditional branch decoded. Its value is meaningless if the latest branch was an unconditional branch. DBRC: this field disables the use of the branch return cache (BRC). BRCV: this field indicates whether or not the branch return cache (BRC) is valid. BRC has only one entry (four instructions). BRCW: this field indicates whether or not the latest branch (JAL, JALR RX, BGEZAL, BGEZALL, BLTZAL, or BLTZALL) caused a write into BRC. It is not affected by any other type of branch. BRCH: this field indicates whether or not the latest branch (JR r31 or JALR rx,r31) has a BRC hit. It not affected by any other type of branch. MP: this field indicates whether or not the latest conditional branch verified was mispredicted. BPMode: this is a read-write field for branch prediction algorithm control. 002 : 2-bit counter scheme 01 2 : all conditional branches are predicted not taken 10 2 : all conditional branches are predicted taken 11 2 : forward conditional branches are predicted not taken and backward conditional branches are predicted taken. The default mode is 00 on processor reset. MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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Page 249 and 250: 13. Packaging The R10000 microproce
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Page 253 and 254: Packaging 223 Figure 13-1 R10000 59
Page 255 and 256: Packaging 225 Table 13-3 (cont.) Si
Page 261 and 262: Packaging 231 Figure 13-3 599LGA PW
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Page 265 and 266: 14. Coprocessor 0 This chapter desc
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Page 269 and 270: Coprocessor 0 239 14.3 EntryLo0 (2)
Page 271 and 272: Coprocessor 0 241 14.4 Context (4)
Page 273 and 274: Coprocessor 0 243 14.6 Wired Regist
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Page 277 and 278: Coprocessor 0 247 CU2 CU2 CU1 CU1 C
Page 279 and 280: Coprocessor 0 249 Diagnostic Status
Page 281 and 282: Coprocessor 0 251 Coprocessor Acces
Page 283 and 284: Coprocessor 0 253 Table 14-13 Cause
Page 285 and 286: Coprocessor 0 255 14.13 Processor R
Page 287 and 288: Coprocessor 0 257 14.15 Load Linked
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Page 303 and 304: Coprocessor 0 273 14.21 ECC Registe
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Floating-Point Unit 311 Loading the
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Floating-Point Unit 313 Moves and C
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16. Memory Management This section
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Memory Management 317 Addressing Mo
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Memory Management 319 32-bit User M
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Memory Management 321 32-bit Superv
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Memory Management 323 32-bit Kernel
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Memory Management 325 0X BFFFFFFF 0
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Memory Management 327 64-bit Virtua
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Memory Management 329 Using the TLB
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17. CPU Exceptions This chapter des
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CPU Exceptions 333 17.3 TLB Refill
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CPU Exceptions 335 Priority of Exce
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CPU Exceptions 337 Soft † Reset E
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CPU Exceptions 339 NMI Exception Ca
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CPU Exceptions 341 TLB Exceptions T
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CPU Exceptions 343 TLB Invalid Exce
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CPU Exceptions 345 Cache Error Exce
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CPU Exceptions 347 Integer Overflow
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CPU Exceptions 349 System Call Exce
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CPU Exceptions 351 Reserved Instruc
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CPU Exceptions 353 Floating-Point E
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CPU Exceptions 355 Interrupt Except
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CPU Exceptions 357 17.5 COP0 Instru
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18. Cache Test Mode The R10000 proc
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Cache Test Mode 361 18.3 Entering C
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Cache Test Mode 363 18.5 SysAD(63:0
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Cache Test Mode 365 Auto-Increment
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Cache Test Mode 367 Auto-Increment
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A. Glossary The following terms are
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A.6 Dynamic Scheduling The R10000 p
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A.11 Nonblocking Loads and Stores M
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A.13 Logical and Physical Registers
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Index I-1 Index Numerics 16-word, c
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Index I-3 uncached accelerated, des
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Index I-5 branch on CP0 instruction
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Index I-7 F fetch pipeline 6, 17 fe
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Index I-9 TLBWR 285, 300 unsupporte
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Index I-11 NMI see also nonmaskable
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Index I-13 CP0 (description of) 235
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Index I-15 SysAD[20:16] interrupt r
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Index I-17 SysWrRdy, signal 41, 118
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