MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

260 Chapter 14.
14.18 FrameMask Register (21)
The FrameMask register is new with the R10000 processor. It masks bits of the
EntryLo0 and EntryLo1 registers so that these masked bits are not passed to the TLB
while doing a TLB write (either TLBWI or TLBWR).
A zero in the FrameMask register allows its corresponding bit in the EntryLo[1,0]
registers to pass to the TLB; a one in the FrameMask register masks off its
corresponding bit in the EntryLo registers and passes a zero to the TLB. Bits 15:0
of the FrameMask register control bits 33:18 of the EntryLo registers.
The remaining bits of this register are ignored on write and read as zeroes. The
content of this register is set to zero after a processor reset or a power-up event.
Figure 14-20 shows the FrameMask register format.
31
FrameMask Register
0 0
Mask bits, PA[39:24]
Figure 14-20 FrameMask Register Format
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
16
16 16
15
0