MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

254 Chapter 14.
14.12 Exception Program Counter (14)
The Exception Program Counter (EPC) † is a read/write register that contains the
address at which processing resumes after an exception has been serviced.
For synchronous exceptions, the EPC register contains either:
• the virtual address of the instruction that was the direct cause of the
exception, or
• the virtual address of the immediately preceding branch or jump
instruction (when the instruction is in a branch delay slot, and the
Branch Delay bit in the Cause register is set).
The processor does not write to the EPC register when the EXL bit in the Status
register is set to a 1.
Figure 14-14 shows the format of the EPC register.
EPC Register
63 0
Figure 14-14 EPC Register Format
† The ErrorEPC register provides a similar capability, described later in this chapter.
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
EPC
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